DA82562EZ Intel, DA82562EZ Datasheet - Page 17

• Manufacturer Part Number: DA82562EZ
• Description: 10/100 Mbps Platform LAN Connect
• Manufacturer: Intel

The MLT-3 encoder receives the scrambled Non-Return to Zero (NRZ) data stream from the scrambler and encodes
the stream into MLT-3 for presentation to the driver. MLT-3 is similar to NRZ1 coding, but three levels are output
instead of two. The three output levels are positive, negative and zero. When an NRZ “0” arrives at the input of the
encoder, the last output level is maintained (either positive, negative or zero). When an NRZ “1” arrives at the input
of the encoder, the output steps to the next level. The order of steps is negative-zero-positive-zero which continues
periodically. Refer to IEEE 802.3 Specification for further details.
4.1.1.3
The 82562EZ does not differentiate between the fields of the MAC frame containing preamble, start of frame
delimiter, data and Cyclic Redundancy Check (CRC). The 82562 encodes the first byte of the preamble as the “JK”
symbol, encodes all other pieces of data according to the 4B/5B lookup table, and adds the “TR” code after the end
of the packet. The 82562 scrambles and serializes the data into a 125 Mbps stream, encodes it as MLT-3, and drives
it onto the wire.
4.1.1.4
The transmit differential lines are implemented with a digital slope controlled current driver that meets Twisted Pair
Physical Media Device (TP-PMD) specifications. Current is sunk from the isolation transformer by the transmit
differential pins. The conceptual transmit differential waveform for 100 Mbps is illustrated in the following figure.
The magnetics module external to the 82562EZ converts I
specification. The same magnetics used for 100BASE-TX mode can also work in 10BASE-T mode.
4.1.2
The receive subsection of the 82562EZ accepts 100BASE-TX MLT-3 data on the receive differential pair. Due to
the advanced digital signal processing design techniques employed, the 82562EZ will accurately receive valid data
from Category 5 (CAT5) UTP and Type 1 STP cable of length well in excess of 100 meters.
4.1.2.1
The distorted MLT-3 signal at the end of the wire is restored by the equalizer. The equalizer performs adaptation
based on the shape of the received signal, equalizing the signal to meet superior data dependent jitter performance.
4.1.2.2
The clock recovery circuit uses advanced digital signal processing technology to compensate for various signal
jitter causes. The circuit recovers the 125 MHz clock and data and presents the data to the MLT-3 decoder.
Datasheet
Figure 3. Conceptual Transmit Differential Waveform
100BASE-TX Transmit Framing
Transmit Driver
100BASE-TX Receive Blocks
Adaptive Equalizer
Receive Clock and Data Recovery
TDP
and I
TDN
to 2.0 V
Networking Silicon — 82562EZ
PP
, as required by the TP-PMD
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