DA82562EZ Intel, DA82562EZ Datasheet - Page 16
DA82562EZ
Manufacturer Part Number
DA82562EZ
Description
10/100 Mbps Platform LAN Connect
Manufacturer
Intel
Datasheet
1.DA82562EZ.pdf
(40 pages)
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82562EZ — Networking Silicon
4.1.1.2
Data is scrambled in 100BASE-TX in order to reduce electromagnetic emissions during long transmissions of high-
frequency data codes. The scrambler logic accepts 5 bits from the 4B/5B encoder block and presents the scrambled
data to the MLT-3 encoder. The 82562EZ implements the 11-bit stream cipher scrambler as adopted by the ANSI
XT3T9.5 committee for UTP operation. The cipher equation used is:
X[n] = X[n-11] + X[n-9] (mod 2)
10
100BASE-TX Scrambler and MLT-3 Encoder
Symbol
A
B
C
D
E
K
R
V
V
V
V
H
V
V
V
V
V
V
6
7
8
9
F
J
T
I
5B Symbol Code
10010
10011
10110
11010
11000
10001
01101
00000
00001
00010
00011
00100
00101
00110
01000
01100
10000
11001
01110
01111
10111
11011
11100
11101
00111
11111
Inter Packet Idle Symbol
(No 4B)
1st Start of Packet Symbol
0101
2nd Start of Packet Symbol
0101
1st End of Packet Symbol
2nd End of Packet Symbol
and Flow Control
INVALID
INVALID
INVALID
INVALID
INVALID
INVALID
INVALID
INVALID
INVALID
Flow Control S
INVALID
4B Nibble Code
0110
1000
1001
1010
1011
1100
1101
0111
1110
1111
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