EVAL-ADAU1701EB AD [Analog Devices], EVAL-ADAU1701EB Datasheet - Page 20

• Manufacturer Part Number: EVAL-ADAU1701EB
• Description: SigmaDSP 28/56-Bit Audio Processor with 2ADC/4DAC
• Manufacturer: AD [Analog Devices]

ADAU1701
line low during the ninth clock pulse. This ninth bit is known as
an acknowledge bit. All other devices withdraw from the bus at
this point and return to the idle condition. The R/ W bit
determines the direction of the data. A logic 0 on the LSB of the
first byte means the master will write information to the
peripheral. A logic 1 on the LSB of the first byte means the
master will read information from the peripheral. A data
transfer takes place until a stop condition is encountered. A stop
condition occurs when SDA transitions from low to high while
SCL is held high. Figure 22 shows the timing of an I
Burst mode addressing, where the subaddresses are automati-
cally incremented at word boundaries, can be used for writing
large amounts of data to contiguous memory locations. This
increment happens automatically if a stop condition is not
encountered after a single-word write. The registers and
memories in the ADAU1701 range in width from one to five
bytes, so the autoincrement feature knows the mapping between
sub-addresses and the word length of the destination register
(or memory location). A data transfer is always terminated by a
stop condition.
Stop and start conditions can be detected at any stage during
the data transfer. If these conditions are asserted out of
sequence with normal read and write operations, these cause an
immediate jump to the idle condition. During a given SCL high
period, the user should only issue one start condition, one stop
condition, or a single stop condition followed by a single start
condition. If an invalid subaddress is issued by the user, the
ADAU1701 does not issue an acknowledge and returns to the
idle condition. If the user exceeds the highest subaddress while
in autoincrement mode, one of two actions will be taken. In
read mode, the ADAU1701 outputs the highest subaddress
register contents until the master device issues a no-
acknowledge, indicating the end of a read. A no-acknowledge
condition is where the SDA line is not pulled low on the ninth
clock pulse on SCL. If the highest subaddress location is
reached while in write mode, the data for the invalid byte is not
loaded into any subaddress register, a no-acknowledge is issued
by the ADAU1701, and the part returns to the idle condition.
I
Figure 24 shows the timing of a single-word write operation.
Every ninth clock, the ADAU1701 issues an acknowledge by
pulling SDA low.
Figure 25 shows the timing of a burst mode write sequence.
This figure shows an example where the target destination
registers are two bytes. The ADAU1701 knows to increment its
subaddress register every two bytes because the requested
subaddress corresponds to a register or memory area with a
2-byte word length.
The timing of a single word read operation is shown in
Figure 26. Note that the first R/ W bit is still a 0, indicating a
2
C Read & Write Operations
2
C write.
Rev. PrF | Page 20 of 43
write operation. This is because the subaddress still needs to be
written in order to set up the internal address. After the
ADAU1701 acknowledges the receipt of the subaddress, the
master must issue a repeated start command followed by the
chip address byte with the R/ W set to 1 (read). This causes the
ADAU1701’s SDA to turn around and begin driving data back
to the master. The master then responds every ninth pulse with
an acknowledge pulse to the ADAU1701.
Figure 27 shows the timing of a burst-mode read sequence. This
figure shows an example where the target read registers are two
bytes. The ADAU1701 knows to increment its subaddress
register every two bytes because the requested subaddress
corresponds to a register or memory area with word lengths of
two bytes. Other address ranges may have a variety of word
lengths ranging from one to five bytes; the ADAU1701 always
decodes the subaddress and sets the autoincrement circuit so
that the address increments after the appropriate number of
bytes.
SPI PORT
By default, the ADAU1701 is in I
SPI control mode by pulling CLATCH/WP low three times.
The SPI port uses a 4-wire interface, consisting of CLATCH,
CCLK, CDATA, and COUT signals. The CLATCH signal goes
low at the beginning of a transaction and high at the end of a
transaction. The CCLK signal latches CDATA on a low-to-high
transition. COUT data is shifted out of the ADAU1701 on the
falling edge of CCLK and should be clocked into the receiving
device, such as a microcontroller, on CCLK’s rising edge. The
CDATA signal carries the serial input data, and the COUT
signal is the serial output data. The COUT signal remains three-
stated until a read operation is requested. This allows other SPI-
compatible peripherals to share the same readback line. All SPI
transactions follow the same basic format, shown in Table 17. A
timing diagram is shown in Figure 39. All data written should
be MSB-first.
Table 17. Generic Control Word Format
Byte 0
chip_adr [6:0],
R/W
Chip Address R/ W
The first byte of an SPI transaction includes the 7-bit chip
address and a R/ W bit. The chip address is set by the ADR_SEL
pin. This allows two ADAU1701s to share a CLATCH signal,
yet still operate independently. When ADR_SEL0 is low, the
chip address is 0000000; when it is high, the address is 0000001.
The LSB of this first byte determines whether the SPI
transaction is a read (Logic Level 1) or a write (Logic Level 0).
Byte 1
0000,
subadr
[11:8]
Preliminary Technical Data
Byte 2
subadr[7:0]
2
C mode, but can be put into
Byte 3
data
Byte 4,
etc.
data