EVAL-ADAU1701EB AD [Analog Devices], EVAL-ADAU1701EB Datasheet - Page 25

• Manufacturer Part Number: EVAL-ADAU1701EB
• Description: SigmaDSP 28/56-Bit Audio Processor with 2ADC/4DAC
• Manufacturer: AD [Analog Devices]

Preliminary Technical Data
SIGNAL PROCESSING
OVERVIEW
The ADAU1701 is designed to provide all signal processing
functions commonly used in stereo or multichannel playback
systems. The signal processing flow is designed using the ADI-
supplied SigmaStudio software, which allows graphical entry
and real-time control of all signal processing functions.
Many of the signal processing functions are coded using full,
56-bit double-precision arithmetic. The input and output word
lengths are 24 bits. Four extra headroom bits are used in the
processor to allow internal gains up to 24 dB without clipping.
Additional gains can be achieved by initially scaling down the
input signal in the signal flow.
The signal processing blocks can be arranged in a custom pro-
gram that can be loaded to the ADAU1701’s RAM. The
available signal processing blocks are explained in the following
sections.
NUMERIC FORMATS
It is common in DSP systems to use a standardized method of
specifying numeric formats. Fractional number systems are
specified by an A.B format, where A is the number of bits to the
left of the decimal point and B is the number of bits to the right
of the decimal point.
The ADAU1701 uses the same numeric format for both the
coefficient values (stored in the parameter RAM) and the signal
data values. The format is as follows:
Numerical Format: 5.23
Range: –16.0 to (+16.0 − 1 LSB)
Examples:
1000 0000 0000 0000 0000 0000 0000 = –16.0
1110 0000 0000 0000 0000 0000 0000 = –4.0
1111 1000 0000 0000 0000 0000 0000 = –1.0
Rev. PrF | Page 25 of 43
1111 1110 0000 0000 0000 0000 0000 = –0.25
1111 1111 1111 1111 1111 1111 1111 = (1 LSB below 0.0)
0000 0000 0000 0000 0000 0000 0000 = 0.0
0000 0010 0000 0000 0000 0000 0000 = 0.25
0000 1000 0000 0000 0000 0000 0000 = 1.0
0010 0000 0000 0000 0000 0000 0000 = 4.0
0111 1111 1111 1111 1111 1111 1111 = (16.0 – 1 LSB).
The serial port accepts up to 24 bits on the input and is sign-
extended to the full 28 bits of the core. This allows internal
gains of up to 24 dB without encountering internal clipping.
A digital clipper circuit is used between the output of the DSP
core and the outputs (see Figure 30). This clips the top four bits
of the signal to produce a 24-bit output with a range of 1.0
(minus 1 LSB) to –1.0.
PROGRAMMING
On power-up, the ADAU1701’s default program passes the
unprocessed input signals to the outputs (Figure 15), but the
outputs are muted by default (see Power-Up Sequence section).
There are 1,024 instruction cycles per audio sample, resulting in
an internal clock rate of 49.152 MHz (for f
runs in a stream-oriented manner, meaning all 1,024
instructions are executed each sample period. The ADAU1701
may also be set up to accept double or quad-speed inputs by
reducing the number of instructions/sample, which can be set
in the core control register.
The part can be programmed easily using SigmaStudio, a
graphical tool provided by Analog Devices. No knowledge of
writing line-level DSP code is required.
DATA IN
Figure 30. Numeric Precision and Clipping Structure
SERIAL PORT
4-BIT SIGN EXTENSION
1.23
5.23
SIGNAL PROCESSING
(5.23 FORMAT)
s
= 48 kHz). This DSP
5.23
ADAU1701
CLIPPER
DIGITAL
1.23