EVAL-ADAU1701EB AD [Analog Devices], EVAL-ADAU1701EB Datasheet - Page 34

• Manufacturer Part Number: EVAL-ADAU1701EB
• Description: SigmaDSP 28/56-Bit Audio Processor with 2ADC/4DAC
• Manufacturer: AD [Analog Devices]

ADAU1701
Table 46. Serial Output Control Register (2078)
Register Bits
15:14
13
12
11
10:9
8:7
6
5
4:2
1:0
Function
Unused
OUTPUT_LRCLK Polarity
0 = Frame Begins on Falling Edge
1 = Frame Begins on Rising Edge
OUTPUT_BCLK Polarity
0 = Data Changes on Falling Edge
1 = Data Changes on Rising Edge
Master/Slave
0 = Slave
1 = Master
OUTPUT_BCLK Frequency (Master Mode only)
00 = core_clock/16
01 = core_clock/8
10 = core_clock/4
11 = core_clock/2
OUTPUT_LRCLK (Master Mode only)
00 = core_clock/1024
01 = core_clock/512
10 = core_clock/256
Frame Sync Type
0 = LRCLK
1 = Pulse
Serial Output/TDM Mode Control
0 = 8 Serial Data Outputs
1 = Enable TDM on SDATA_OUTx
MSB Position
000 = Delay by 1
001 = Delay by 0
010 = Delay by 8
011 = Delay by 12
100 = Delay by 16
101 Reserved
111 Reserved
Output Word Length
00 = 24 Bits
01 = 20 Bits
10 = 16 Bits
11 = Reserved
Rev. PrF | Page 34 of 43
SERIAL OUTPUT CONTROL REGISTERS
OUTPUT_LRCLK Polarity (Bit 13)
When set to 0, the left channel data is clocked when
OUTPUT_LRCLK is low, and the right channel data clocked
when OUTPUT_LRCLK is high. When set to 1, the right
channel data is clocked when OUTPUT_LRCLK is low, and the
left channel data clocked when OUTPUT_LRCLK is high.
OUTPUT_BCLK Polarity (Bit 12)
This bit controls on which edge of the bit clock the output data
is clocked. Data changes on the falling edge of OUTPUT_BCLK
when this bit is set to 0, and on the rising edge when this bit is
set at 1.
Master/Slave (Bit 11)
This bit sets whether the output port is a clock master or slave.
The default setting is slave; on power-up, Pins OUTPUT_BCLK
and OUTPUT_LRCLK are set as inputs until this bit is set to 1,
at which time they become clock outputs.
OUTPUT_BCLK Frequency (Bits 10:9)
When the output port is being used as a clock master, these bits
set the frequency of the output bit clock, which is divided down
from the internal 49.152 MHz core clock.
OUTPUT_LRCLK Frequency (Bits 8:7)
When the output port is used as a clock master, these bits set
the frequency of the output word clock on the
OUTPUT_LRCLK pins, which is divided down from the
internal 49.152 MHz
core clock.
Frame Sync Type (Bit 6)
This bit sets the type of signal on the OUTPUT_LRCLK pins.
When set to 0, the signal is a word clock with a 50% duty cycle;
when set to 1, the signal is a pulse with a duration of one bit
clock at the beginning of the data frame.
Serial Output/TDM Mode Control (Bit 5)
Setting this bit to 1 changes the output port from multiple serial
outputs to a single TDM output stream on the appropriate
SDATA_OUTx pin. This bit must be set in both serial output
control registers to enable 16-channel TDM on SDATA_OUT0.
MSB Position (Bits 4:2)
These three bits set the position of the MSB of data with respect
to the LRCLK edge. The data output of the ADAU1701 is always
MSB first.
Output Word Length (Bits 1:0)
These bits set the word length of the output data-word. All bits
following the LSB are set to 0.
Preliminary Technical Data