EVAL-ADAU1701EB AD [Analog Devices], EVAL-ADAU1701EB Datasheet - Page 33

• Manufacturer Part Number: EVAL-ADAU1701EB
• Description: SigmaDSP 28/56-Bit Audio Processor with 2ADC/4DAC
• Manufacturer: AD [Analog Devices]

Preliminary Technical Data
In TDM mode, the ADAU1701 can be a master for 48 kHz and
96 kHz data, but not for 192 kHz data. Table 43 displays the
modes in which the serial output port will function.
Table 43. Serial Output Port Master/Slave Mode Capabilities
The output control registers give the user control of clock
polarities, clock frequencies, clock types, and data format. In all
modes except for the right-justified modes (MSB delayed by 8,
12, or 16), the serial port accepts an arbitrary number of bits up
to a limit of 24. Extra bits will not cause an error, but will be
truncated internally. Proper operation of the right-justified
modes requires the LSB to align with the edge of the LRCLK.
The default settings of all serial port control registers
correspond to 2-channel I
both master and slave modes unless otherwise noted.
The functions of the individual multi-purpose pins in serial
data port mode are shown in Table 44. Pins MP0-5 support
digital data input to the ADAU1701 and pins MP6-11 handle
digital data output from the DSP. The configuration of the serial
data input port is set in the Serial Input Control Register (Table
47) and the output port is controlled with the Serial Output
Control Register (Table 46). The input port clocks function only
as slaves and the output port clocks can be set to be either
master or slave. The INPUT_LRCLK and INPUT_BCLK pins
(MP4 & MP5) are used to clock the SDATA_INx signals (MP0-
Table 45. Data Format Configurations
Format
I
Left-Justified
(Figure 33)
Right-Justified
(Figure 34)
TDM with Clock
(Figure 35)
TDM with Pulse
(Figure 36)
2
S (Figure 32)
f
48 kHz
96 kHz
192 kHz
S
LRCLK Polarity
Frame begins on
falling edge
Frame begins on
rising edge
Frame begins on
rising edge
Frame begins on
falling edge
Frame begins on
rising edge
2-Channel Modes
(I
Master and slave
Master and slave
Master and slave
2
S, LJ, RJ)
2
S mode. All register settings apply to
LRCLK Type
Clock
Clock
Clock
Clock
Pulse
8-Channel
TDM
Master and
slave
Master and
slave
Slave only
BCLK Polarity
Data changes on falling edge
Data changes on falling edge
Data changes on falling edge
Data changes on falling edge
Data changes on falling edge
Rev. PrF | Page 33 of 43
3) and the OUTPUT_LRCLK and OUTPUT BCLK (MP10 &
MP11) are used to clock the SDATA_OUTx signals (MP6-9).
If an external ADC will be connected as a slave to the
ADAU1701, both the input and output port clocks will need to
be used. The output LRCLK and BCLK (MP10 & MP11) will
need to be set into master mode and connected externally to the
input LRCLK and BCLK pins (MP4 & MP5) and the external
ADC’s clock input pins. The data will be output from the
external ADC into the SigmaDSP on one of the four SDATA_IN
pins (MP0-3).
Connections to an external DAC are handled exclusively with
the output port pins. The output LRCLK and BCLK can be set
to be either master or slave, and the SDATA_OUT pins are used
to output data from the SigmaDSP to the external DAC.
Table 45 shows the proper configurations for standard audio
data formats.
Table 44. Multi-Purpose Pin Serial Data Port Functions
Multipurpose Pin
MP0
MP1
MP2
MP3
MP4
MP5
MP6
MP7
MP8
MP9
MP10
MP11
MSB Position
Delayed from start of word clock by one BCLK
Delayed from start of word clock by one BCLK
Delayed from LRCLK edge by one BCLK
Aligned with LRCLK edge
Delayed from LRCLK edge by 8, 12, or 16 BCLKs
Function
SDATA_IN0/TDM_IN
SDATA_IN1
SDATA_IN2
SDATA_IN3
INPUT_LRCLK (slave only)
INPUT_BCLK (slave only)
SDATA_OUT0/TDM_OUT
SDATA_OUT1
SDATA_OUT2
SDATA_OUT3
OUTPUT_LRCLK (master or slave)
OUTPUT_BCLK (master or slave)
ADAU1701