EVAL-ADAU1701EB AD [Analog Devices], EVAL-ADAU1701EB Datasheet - Page 6

• Manufacturer Part Number: EVAL-ADAU1701EB
• Description: SigmaDSP 28/56-Bit Audio Processor with 2ADC/4DAC
• Manufacturer: AD [Analog Devices]

ADAU1701
t
t
t
t
t
t
t
SPI PORT
t
t
t
t
t
t
t
t
I
MULTIPURPOSE PINS & RESET
t
PLL
Table 7.
Parameter
Operating Range
Lock Time
REGULATOR
Table 8.
Parameter
DVDD Voltage
1
f
t
t
t
t
t
t
t
t
t
t
t
t
t
2
SIS
SIH
LOS
LOH
TS
SODS
SODM
CCPL
CCPH
CLS
CLH
CLPH
CDS
CDH
COD
RLPW
SCL
SCLH
SCLL
SCS
SCH
DS
SCR
SCF
SDR
SDF
BFT
GRT
GFT
GIL
Regulator specifications are calculated using an FZT953 transistor in the circuit.
C PORT
1
Table 45.
All timing specifications are given for the default (I
SDATA_INx Setup
SDATA_INx Hold
OUTPUT_LRCLK Setup
OUTPUT_LRCLK Hold
OUTPUT_BCLK Falling to
OUTPUT_LRCLK Timing Skew
SDATA_OUTx Delay
SDATA_OUTx Delay
CCLK Pulse Width LO
CCLK Pulse Width HI
CLATCH Setup
CLATCH Hold
CLATCH Pulse Width HI
CDATA Setup
CDATA Hold
COUT Delay
SCL Clock Frequency
SCL High
SCL Low
Setup Time
Hold Time
Data Setup Time
SCL Rise Time
SCL Fall Time
SDA Rise Time
SDA Fall Time
Bus-Free Time
GPIO Rise Time
GPIO Fall Time
GPIO Input Latency
RESETB LO Pulse Width
1
To BCLK_IN rising
From BCLK_IN rising
Slave mode
Slave mode
Slave mode, from OUTPUT_BCLK falling
Master mode, from OUTPUT_BCLK falling
To CCLK rising
From CCLK rising
To CCLK rising
From CCLK rising
From CCLK rising
Relevant for Repeated Start Condition
After this period the 1st clock is generated
Between Stop and Start
Until high/low value read by core
2
S) states of the serial input control port and the serial output control ports. See
Min
TBD
Min
Rev. PrF | Page 6 of 43
Typ
Typ
1.8
10
10
10
10
TBD
TBD
TBD
TBD
TBD
TBD
TBD
0.6
1.3
0.6
100
0.6
20
0.6
Preliminary Technical Data
Max
Max
TBD
20
40
40
TBD
400
300
300
300
300
TBD
TBD
1.5 × 1/fs
Unit
MHz
ms
Unit
V
ns
ns
ns
ns
ns
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
μs
μs
μs
ns
ns
ns
ns
ns
ns
μs
ns