S71PL032J SPANSION [SPANSION], S71PL032J Datasheet - Page 151

• Manufacturer Part Number: S71PL032J
• Description: STACKED MULTI CHIP PRODUCT FLASH MEMORY AND RAM
• Manufacturer: SPANSION [SPANSION]

Note: Both t
t
Notes:
1. The all address inputs must be High from Cycle #1 to #5.
2. The address key must confirm the format specified in page 136. If not, the operation and data are not guaranteed.
3. After t
November 2, 2004 pSRAM_Type07_13_A1
RC
(min) period for Standby mode from CE1# Low to High transition.
LB#, UB#
ADDRESS
DQ*
CE1#
WE#
OE#
CE1#
OE#
WE#
CP
3
following Cycle #6, the Power Down Program is completed and returned to the normal operation.
CHOX
and t
Cycle #1
MSB*
CHWX
t
RC
Active (Read)
Figure 78. Power Down Program Timing (for 32M/64M Only)
RDa
1
A d v a n c e
define the earliest entry timing for Standby mode. If either of timing is not satisfied, it takes
Figure 77. Standby Entry Timing after Read or Write
t
CP
Cycle #2
t
MSB*
CHOX
t
WC
RDa
1
i n f o r m a t i o n
t
CP
Standby
Cycle #3
MSB*
pSRAM Type 7
t
WC
RDa
1
t
CP
Cycle #4
MSB*
t
WC
Active (Write)
X
1
t
CP
Cycle #5
MSB*
t
t
CHWX
WC
X
1
t
CP
Cycle #6
Standby
Key*
t
RC
RDb
2
t
CP
*
3
151