S71PL032J SPANSION [SPANSION], S71PL032J Datasheet - Page 33

• Manufacturer Part Number: S71PL032J
• Description: STACKED MULTI CHIP PRODUCT FLASH MEMORY AND RAM
• Manufacturer: SPANSION [SPANSION]

Read
Write
Standby
Output Disable
Reset
Temporary Sector Unprotect (High Voltage)
Device Bus Operations
Legend: L= Logic Low = V
Sector Address, A
Notes:
1. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the
2. WP#/ACC must be high when writing to upper two and lower two sectors.
August 12, 2004 S29PL127J_064J_032J_MCP_00_A3
High Voltage Sector Protection section.
Requirements for Reading Array Data
Operation
This section describes the requirements and use of the device bus operations,
which are initiated through the internal command register. The command register
itself does not occupy any addressable memory location. The register is a latch
used to store the commands, along with the address and data information
needed to execute the command. The contents of the register serve as inputs to
the internal state machine. The state machine outputs dictate the function of the
device. Table
require, and the resulting output. The following subsections describe each of
these operations in further detail.
To read array data from the outputs, the system must drive the OE# and appro-
priate CE# pins. OE# is the output control and gates array data to the output
pins. WE# should remain at V
The internal state machine is set for reading array data upon device power-up,
or after a hardware reset. This ensures that no spurious alteration of the memory
content occurs during the power transition. No command is necessary in this
mode to obtain array data. Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid data on the device data
outputs. Each bank remains enabled for read access until the command register
contents are altered.
Refer to Table
I
reading array data.
Random Read (Non-Page Read)
Address access time (t
output data. The chip enable access time (t
dresses and stable CE# to valid data at the output inputs. The output enable
CC1
IN
= Address In, D
in the DC Characteristics table represents the active current specification for
A d v a n c e
IL
, H = Logic High = V
1
23
lists the device bus operations, the inputs and control levels they
for timing specifications and to
Table 1. PL127J Device Bus Operations
IN
S29PL127J/S29PL064J/S29PL032J for MCP
ACC
= Data In, D
0.3 V
V
CE#
) is equal to the delay from stable addresses to valid
IO
X
X
L
L
L
I n f o r m a t i o n
±
IH
.
IH
, V
OE#
OUT
H
X
H
X
X
L
ID
= Data Out
= 11.5-12.5 V, V
WE#
CE
H
X
H
X
X
L
) is the delay from the stable ad-
Figure 11
RESET#
0.3 V
V
V
IO
H
H
H
L
ID
±
for the timing diagram.
HH
= 8.5-9.5 V, X = Don’t Care, SA =
X (Note 2)
X (Note 2)
WP#/ACC
X
X
X
X
(Amax–A0)
Addresses
A
A
A
X
X
X
IN
IN
IN
High-Z
High-Z
High-Z
DQ15–
D
DQ0
D
D
OUT
IN
IN
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