S71WS512NB0BAEZZ0 SPANSION [SPANSION], S71WS512NB0BAEZZ0 Datasheet - Page 101
S71WS512NB0BAEZZ0
Manufacturer Part Number
S71WS512NB0BAEZZ0
Description
Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt
Manufacturer
SPANSION [SPANSION]
Datasheet
1.S71WS512NB0BAEZZ0.pdf
(142 pages)
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FUNCTIONAL DESCRIPTION (Continued)
June 28, 2004 S71WS512NE0BFWZZ_00_A1
Burst Read Operation
Burst Write Operation
Burst Read/Write Operation
ADDRESS
ADDRESS
CLK
ADV#
CE#1
OE#
WE#
DQ
WAIT#
CLK
ADV#
CE#1
OE#
WE#
DQ
WAIT#
Synchronous burst read/write operation provides faster memory access that
synchronized to microcontroller or system bus frequency. Configuration Register
Set is required to perform burst read & write operation after power-up. Once CR
Set sequence is performed to select synchronous burst mode, the device is
configured to synchronous burst read/write operation mode with corresponding
RL and BL that is set through CR Set sequence together with operation mode. In
order to perform synchronous burst read & write operation, it is required to control
new signals, CLK, ADV# and WAIT# that Low Power SRAMs don’t have.
High
High-Z
High-Z
High
High-Z
High-Z
Valid
Valid
P r e l i m i n a r y
RL
RL-1
128Mb pSRAM
D
1
BL
Q
D
1
2
BL
Q
2
D
BL
Q
BL
101
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