S71WS512NB0BAEZZ0 SPANSION [SPANSION], S71WS512NB0BAEZZ0 Datasheet - Page 92

• Manufacturer Part Number: S71WS512NB0BAEZZ0
• Description: Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt
• Manufacturer: SPANSION [SPANSION]

Wait State Configuration Register Setup:
DQ13, DQ12, DQ11 = “111” ⇒ Reserved
DQ13, DQ12, DQ11 = “110” ⇒ Reserved
DQ13, DQ12, DQ11 = “101” ⇒ 5 programmed, 7 total
DQ13, DQ12, DQ11 = “100” ⇒ 4 programmed, 6 total
DQ13, DQ12, DQ11 = “011” ⇒ 3 programmed, 5 total
DQ13, DQ12, DQ11 = “010” ⇒ 2 programmed, 4 total
DQ13, DQ12, DQ11 = “001” ⇒ 1 programmed, 3 total
DQ13, DQ12, DQ11 = “000” ⇒ 0 programmed, 2 total
Note:
“101”.
Note:
checking the status of the program or erase operation in the “busy” bank. The system should read status twice to ensure
valid information.
92
Figure assumes address DQ0 is not at an address boundary, active clock edge is rising, and wait state is set to
Breakpoints in waveforms indicate that system may alternately read array data from the “non-busy bank” while
Addresses
AVD#
AVD#
Data
WE#
OE#
Data
CE#
OE#
CLK
t WP
Command Sequence
Figure 31. Back-to-Back Read/Write Cycle Timings
PA/SA
t AS
S29WSxxxN MirrorBit™ Flash Family For Multi-chip Products (MCP) S71WS512NE0BFWZZ_00_ A1 June 28, 2004
Last Cycle in
Sector Erase
Program or
Figure 30. Example of Wait States Insertion
t WC
1
t W
PD/30h
t AH
t DS
0
2
A d v a n c e
t OEH
t OE
t D
t SR/
RA
Read status (at least two cycles) in same bank
t ACC
t RC
3
1
and/or array data from other bank
RD
following addresses being latched
t OEZ
total number of clock cycles
4
2
following last wait state triggers
I n f o r m a t i o n
Rising edge of next clock cycle
t OEH
number of clock cycles
programmed
5
3
RA
next burst data
t RC
4
6
RD
t GHWL
7
5
command sequence
write or program
Begin another
555h
D0
t WC
AAh
D1