S71WS512NB0BAEZZ0 SPANSION [SPANSION], S71WS512NB0BAEZZ0 Datasheet - Page 81
S71WS512NB0BAEZZ0
Manufacturer Part Number
S71WS512NB0BAEZZ0
Description
Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt
Manufacturer
SPANSION [SPANSION]
Datasheet
1.S71WS512NB0BAEZZ0.pdf
(142 pages)
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Notes:
1. Figure shows total number of wait states set to five cycles. The total number of wait states can be
2. If any burst address occurs at “address + 1”, “address + 2”, or “address + 3”, additional clock delay cycles
3. The device is in synchronous mode.
June 28, 2004 S71WS512NE0BFWZZ_00_A1
programmed from two cycles to seven cycles.
are inserted, and are indicated by RDY.
Data (n + 3)
Timing Diagrams
Data (n + 1)
Data (n + 2)
RDY (n + 3)
RDY (n + 1)
RDY (n + 2)
Addresses
Data (n)
RDY (n)
AVD#
OE#
CE#
CLK
Hi-Z
Hi-Z
t AVC
Hi-Z
t ACS
Hi-Z
Figure 13. CLK Synchronous Burst Mode Read (rising active CLK)
A d v a n c e
t ACH
Aa
t CR
1
t CES
S29WSxxxN MirrorBit™ Flash Family For Multi-chip Products (MCP)
t AVD
2
t OE
t IACC
5 cycles for initial access shown.
3
I n f o r m a t i o n
4
18.5 ns typ. (54 MHz)
t RACC
5
t RDYS
Da
Da
Da
Da
6
t BDH
Da + 1
Da + 1
Da + 1
Da
t BACC
7
Da + 2
Da + 2
Da + 1
Da
Da + 3
Da + 2
Da + 1
Da
Da + n
Da + n
Da + n
Da + n
t CEZ
t OEZ
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
81
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