S71WS512NB0BAEZZ0 SPANSION [SPANSION], S71WS512NB0BAEZZ0 Datasheet - Page 84
S71WS512NB0BAEZZ0
Manufacturer Part Number
S71WS512NB0BAEZZ0
Description
Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt
Manufacturer
SPANSION [SPANSION]
Datasheet
1.S71WS512NB0BAEZZ0.pdf
(142 pages)
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AC Characteristics—Asynchronous
Notes:
1. Asynchronous Access Time is from the last of either stable addresses or the falling edge of AVD#.
2. Not 100% tested.
Timing Diagrams
Note:
84
JEDEC
Parameter
RA = Read Address, RD = Read Data.
Asynchronous Mode Read @
Standard
t
t
t
AAVDH
AAVDS
t
t
t
t
AVDP
t
t
ACC
OEH
OEZ
CAS
OE
CE
Addresses
Output Enable Hold Time
AVD#
Figure 18. Asynchronous Mode Read with Latched Addresses
WE#
Data
OE#
CE#
Address Hold Time from Rising Edge of AVD#
Address Setup Time to Rising Edge of AVD#
S29WSxxxN MirrorBit™ Flash Family For Multi-chip Products (MCP) S71WS512NE0BFWZZ_00_ A1 June 28, 2004
Asynchronous Access Time
Output Enable to High Z
Output Enable to Output Valid
Access Time from CE# Low
CE# Setup Time to AVD#
AVD# Low Time
Description
A d v a n c e
t CAS
t OEH
Toggle and Data# Polling
V
t AAVDS
IO
RA
pS = 1.8 V
(Note 2)
t CE
(Note 1)
t ACC
Read
t AVDP
t O
I n f o r m a t i o n
t AAVDH
Valid RD
Max
Max
Max
Max
Min
Min
Min
Min
Min
Min
t OEZ
54 MHz
13.5
70
70
12
10
10
5
7
0
0
66 MHz
11.2
70
70
10
4
6
8
8
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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