S71WS512NB0BAEZZ0 SPANSION [SPANSION], S71WS512NB0BAEZZ0 Datasheet - Page 82

• Manufacturer Part Number: S71WS512NB0BAEZZ0
• Description: Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt
• Manufacturer: SPANSION [SPANSION]

Notes:
1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be
2. If any burst address occurs at “address + 1”, “address + 2”, or “address + 3”, additional clock delay cycles
3. The device is in synchronous mode.
Notes:
1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be
2. If any burst address occurs at “address + 1”, “address + 2”, or “address + 3”, additional clock delay cycles
3. The device is in synchronous mode with wrap around.
4. DQ0–DQ7 in data waveform indicate the order of data within a given 8-word address range, from lowest to
82
programmed from two cycles to seven cycles. Clock is set for active rising edge.
are inserted, and are indicated by RDY.
programmed from two cycles to seven cycles. Clock is set for active rising edge.
are inserted, and are indicated by RDY.
highest. Starting address in figure is the 4th address in range (AC).
Addresses
Addresses
AVD#
Data
AVD#
OE#
CE#
RDY
CLK
Data
OE#
CE#
RDY
CLK
Hi-Z
t AVC
Hi-Z
t ACS
t CR
t CR
t AAS
t ACH
AC
Aa
t AVC
1
t CES
t CAS
t AVD
Figure 15. Eight-word Linear Burst with Wrap Around
t AVD
2
S29WSxxxN MirrorBit™ Flash Family For Multi-chip Products (MCP) S71WS512NE0BFWZZ_00_ A1 June 28, 2004
t AAH
7
1
t OE
cycles for initial access shown.
Figure 14. Synchronous Burst Mode Read
t OE
7 cycles for initial access shown.
3
t IACC
2
t IACC
4
A d v a n c e
3
5
t ACC
4
6
t RACC
5
7
t RDYS
I n f o r m a t i o n
DC
t BDH
6
DD
t BACC
t RACC
7
DE
t RDYS
Da
DF
t BDH
Da + 1
D8
t BACC
DB
Da + n
t CEZ
t OEZ
t RACC
Hi-Z
Hi-Z