AM49DL640BH56IS SPANSION [SPANSION], AM49DL640BH56IS Datasheet
AM49DL640BH56IS
Related parts for AM49DL640BH56IS
AM49DL640BH56IS Summary of contents
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Data Sheet July 2003 The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig- inally developed the specification, these ...
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ADVANCE INFORMATION Am49DL640BH Stacked Multi-Chip Package (MCP) Flash Memory and SRAM Am29DL640H 64 Megabit ( 8-Bit 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 32 Mbit ( 16-Bit) Pseudo Static RAM with Page ...
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GENERAL DESCRIPTION Am29DL640H Features The Am29DL640H megabit, 3.0 volt-only flash memory device, organized as 4,194,304 words of 16 bits each or 8,388,608 bytes of 8 bits each. Word mode data ...
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TABLE OF CONTENTS Continuity of Specifications ...................................................... 1 Continuity of Ordering Part Numbers ....................................... 1 For More Information ................................................................ 1 This page left intentionally blank ...
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Figure 30. Pseudo SRAM Write Cycle—CE1#s Control ................. 54 Write Cycle ............................................................................. 55 Figure 31. Pseudo SRAM Write Cycle—WE# Control .................... 55 Figure 32. Pseudo SRAM Write Cycle— UB#s and LB#s Control................................................................... 56 ...
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PRODUCT SELECTOR GUIDE Part Number Standard Voltage Speed Range Options 56 2.7–3.3 V Max Access Time Page Access Time (pSRAM), N/A ns CE#f Access OE# Access, ...
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FLASH MEMORY BLOCK DIAGRAM Mux A21–A0 RY/BY# A21–A0 STATE RESET# CONTROL WE# & COMMAND CE# REGISTER BYTE# WP#/ACC DQ15–DQ0 A21–A0 Mux ...
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CONNECTION DIAGRAM LB UB A18 A17 G1 ...
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CE#f = Chip Enable (Flash) CE1#s = Chip Enable 1 (pSRAM) CE2s = Chip Enable 2 (pSRAM) OE# = Output Enable (Common) WE# = Write Enable (Common) RY/BY# = Ready/Busy Output UB#s = ...
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ORDERING INFORMATION The order number (Valid Combination) is formed by the following: Am49DL640 AMD DEVICE NUMBER/DESCRIPTION Am49DL640BH Stacked Multi-Chip Package (MCP) Flash Memory and SRAM Am29DL640H 64 Megabit (8 ...
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Table 1. Device Bus Operations—Flash Word Mode, CIOf = V Operation CE#f CE1#s (Notes 1, 2) (Note 7) H Read from L Flash (Note 8) H (Note 7) H Write to Flash L ...
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Table 2. Device Bus Operations—Flash Byte Mode, CIOf = V Operation CE#f CE1#s (Notes 1, 2) (Note 7) H Read from L Flash (Note 8) H (Note 7) H Write to Flash L ...
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FLASH DEVICE BUS OPERATIONS Word/Byte Configuration The CIOf pin controls whether the device data I/O pins operate in the byte or word configuration. If the CIOf pin is set at logic ‘1’, the ...
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may be initiated for simultaneous operation with zero latency and the table represent the cur- CC6 CC7 rent specifications for read-while-program and read- while-erase, respectively. Standby Mode When ...
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Table 3. Am29DL640H Sector Architecture Sector Address Bank Sector A21–A12 SA0 0000000000 SA1 0000000001 SA2 0000000010 SA3 0000000011 SA4 0000000100 SA5 0000000101 SA6 0000000110 SA7 0000000111 SA8 0000001xxx SA9 0000010xxx SA10 0000011xxx Bank ...
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Table 3. Am29DL640H Sector Architecture (Continued) Sector Address Bank Sector A21–A12 SA23 0010000xxx SA24 0010001xxx SA25 0010010xxx SA26 0010011xxx SA27 0010100xxx SA28 0010101xxx SA29 0010110xxx SA30 0010111xxx SA31 0011000xxx SA32 0011001xxx SA33 0011010xxx ...
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Table 3. Am29DL640H Sector Architecture (Continued) Sector Address Bank Sector A21–A12 SA71 1000000xxx SA72 1000001xxx SA73 1000010xxx SA74 1000011xxx SA75 1000100xxx SA76 1000101xxx SA77 1000110xxx SA78 1000111xxx SA79 1001000xxx SA80 1001001xxx SA81 1001010xxx ...
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Table 3. Am29DL640H Sector Architecture (Continued) Sector Address Bank Sector A21–A12 SA119 1110000xxx SA120 1110001xxx SA121 1110010xxx SA122 1110011xxx SA123 1110100xxx SA124 1110101xxx SA125 1110110xxx SA126 1110111xxx SA127 1111000xxx SA128 1111001xxx SA129 1111010xxx ...
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Sector/Sector Block Protection and Unprotection (Note: For the following discussion, the term “sector” applies to both sectors and sector blocks. A sector block consists of two or more adjacent sectors that are protected ...
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the system asserts V on the WP#/ACC pin, the de- IL vice disables program and erase functions in sectors 0, 1, 140, and 141, independently of whether those sectors were protected or ...
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START PLSCNT = 1 RESET Wait 1 µs No First Write Temporary Sector Cycle = 60h? Unprotect Mode Yes Set up sector address Sector Protect: Write 60h to sector address ...
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Figure 2. In-System Sector Protect/Unprotect Algorithms SecSi™ (Secured Silicon) Sector Flash Memory Region The SecSi (Secured Silicon) Sector feature provides a Flash memory region that enables permanent part identification through an Electronic Serial ...
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Low V Write Inhibit CC When V is less than V , the device does not ac- CC LKO cept any write cycles. This protects data during V power-up and power-down. The command ...
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Addresses Addresses (Word Mode) (Byte Mode) 1Bh 36h 1Ch 38h 1Dh 3Ah 1Eh 3Ch 1Fh 3Eh 20h 40h 21h 42h 22h 44h 23h 46h 24h 48h 25h 4Ah 26h 4Ch Addresses Addresses (Word ...
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Table 11. Primary Vendor-Specific Extended Query Addresses Addresses (Word Mode) (Byte Mode) 40h 80h 41h 82h 42h 84h 43h 86h 44h 88h 45h 8Ah 46h 8Ch 47h 8Eh 48h 90h 49h 92h 4Ah ...
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FLASH COMMAND DEFINITIONS Writing specific address and data commands or se- quences into the command register initiates device op- erations. Table 12 defines the valid register command sequences. Writing incorrect address and data ...
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quence. The Exit SecSi Sector command sequence returns the device to normal operation. The SecSi Sector is not accessible when the device is executing an Embedded Program or embedded Erase algorithm. Table 12 ...
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Write Program Command Sequence Data Poll from System Embedded Program algorithm in progress Verify Data? No Increment Address Last Address? Programming Completed Note: See Table 12 for program command sequence. Figure 3. Program ...
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DQ7, DQ6, DQ2, or RY/BY# in the erasing bank. Refer to the Flash Write Operation Status section for infor- mation on these status bits. Once the sector erase operation has begun, only the ...
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Table 12. Am29DL640H Command Definitions Command Sequence (Note 1) Addr Read (Note Reset (Note 7) 1 XXX Word 555 Manufacturer ID 4 Byte AAA Word 555 Device ID (Note 9) ...
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FLASH WRITE OPERATION STATUS The device provides several bits to determine the status of a program or erase operation: DQ2, DQ3, DQ5, DQ6, and DQ7. Table 13 and the following subsections describe the ...
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RY/BY#: Ready/Busy# The RY/BY dedicated, open-drain output pin which indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final ...
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DQ2: Toggle Bit II The “Toggle Bit II” on DQ2, when used with DQ6, indi- cates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or ...
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Status Embedded Program Algorithm Standard Mode Embedded Erase Algorithm Erase Suspended Sector Erase-Suspend- Erase Read Suspend Non-Erase Mode Suspended Sector Erase-Suspend-Program Notes: 1. DQ5 switches to ‘1’ when an Embedded Program or Embedded ...
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ABSOLUTE MAXIMUM RATINGS Storage Temperature Plastic Packages . . . . . . . . . . . . . . . –55°C to +125°C Ambient Temperature with Power Applied ...
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FLASH DC CHARACTERISTICS CMOS Compatible Parameter Parameter Description Symbol I Input Load Current LI I RESET# Input Load Current LIT I Output Leakage Current LO I ACC Input Leakage Current LIA Flash V ...
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pSRAM DC & Operating Characteristics Parameter Parameter Description Symbol I Input Leakage Current LI I Output Leakage Current Operating Current CC1 Page Access Operating I s CC2 Current V Output ...
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FLASH DC CHARACTERISTICS Zero-Power Flash 500 1000 Note: Addresses are switching at 1 MHz Figure 9. I Current vs. Time (Showing Active and Automatic Sleep Currents) ...
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TEST CONDITIONS Device Under Test C L 6.2 kΩ Note: Diodes are IN3064 or equivalent Figure 11. Test Setup KEY TO SWITCHING WAVEFORMS WAVEFORM Don’t Care, Any Change Permitted 3.0 V 1.5 V ...
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pSRAM AC CHARACTERISTICS CE#s Timing Parameter JEDEC Std Description — t CE#s Recover Time CCR CE#f CE1#s CE2s Figure 13. Timing Diagram for Alternating December 5, 2003 ...
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FLASH AC CHARACTERISTICS Read-Only Operations Parameter JEDEC Std. Description t t Read Cycle Time (Note 1) AVAV Address to Output Delay AVQV ACC t t Chip Enable to Output Delay ...
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FLASH AC CHARACTERISTICS Hardware Reset (RESET#) Parameter JEDEC Std RESET# Pin Low (During Embedded Algorithms) t Ready to Read Mode (See Note) RESET# Pin Low (NOT During Embedded t Ready Algorithms) to Read ...
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FLASH AC CHARACTERISTICS Word/Byte Configuration (CIOf) Parameter JEDEC Std Description t t CE#f to CIOf Switching Low or High ELFL/ ELFH t CIOf Switching Low to Output HIGH Z FLQZ t CIOf Switching ...
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FLASH AC CHARACTERISTICS Erase and Program Operations Parameter JEDEC Std Description t t Write Cycle Time (Note 1) AVAV Address Setup Time AVWL AS Address Setup Time to OE# low ...
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FLASH AC CHARACTERISTICS Program Command Sequence (last two cycles Addresses 555h CE#f t GHWL OE# WE Data RY/BY VCS Notes program address, ...
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FLASH AC CHARACTERISTICS Erase Command Sequence (last two cycles Addresses 2AAh CE#f t GHWL OE WE Data 55h RY/BY# t VCS Notes: ...
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FLASH AC CHARACTERISTICS t WC Valid PA Addresses t AH CE#f OE WE# t WPH Valid Data In WE# Controlled Write Cycle Figure 21. Back-to-back Read/Write Cycle Timings ...
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FLASH AC CHARACTERISTICS Addresses CE#f t OEH WE# OE Valid Data DQ6/DQ2 RY/BY# Note Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, ...
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FLASH AC CHARACTERISTICS Temporary Sector Unprotect Parameter JEDEC Std Description t V Rise and Fall Time (See Note) VIDR Rise and Fall Time (See Note) VHH HH RESET# Setup Time ...
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FLASH AC CHARACTERISTICS RESET# SA, A6, A1, A0 Sector/Sector Block Protect or Unprotect Data 60h 1 µs CE#f WE# OE# * For sector protect ...
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FLASH AC CHARACTERISTICS Alternate CE#f Controlled Erase and Program Operations Parameter JEDEC Std Description t t Write Cycle Time (Note 1) AVAV Address Setup Time AVWL Address ...
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FLASH AC CHARACTERISTICS 555 for program 2AA for erase Addresses WE# OE# CE Data t RH RESET# RY/BY# Notes: 1. Figure indicates last two bus cycles of ...
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pSRAM AC CHARACTERISTICS Read Cycle Parameter Description Symbol t Read Cycle Time RC t Address Access Time ACC t Chip Enable Access Time CO t Output Enable Access Time OE t Data Byte ...
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pSRAM AC CHARACTERISTICS Addresses Addresses A3 to A20 CE#1 CE2 OE# WE# LB#, UB# D OUT I/ COE t ACC Notes ...
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pSRAM AC CHARACTERISTICS Addresses A0 to A20 t AS WE# CE CE2 LB#, UB# D High-Z OUT I/ (Note 1) I/ Notes the ...
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pSRAM AC CHARACTERISTICS Write Cycle Parameter Description Symbol t Write Cycle Time WC t Write Pulse Time WP t Chip Enable to End of Write CW t Data Byte Control to End of ...
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pSRAM AC CHARACTERISTICS Addresses A0 to A20 t AS WE# CE CE2 UB#, LB# D High-Z OUT I/ (Note Notes the ...
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FLASH ERASE AND PROGRAMMING PERFORMANCE Parameter Sector Erase Time Chip Erase Time Byte Program Time Accelerated Byte/Word Program Time Word Program Time Byte Mode Chip Program Time (Note 3) Word Mode Notes: 1. ...
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pSRAM DATA RETENTION Parameter Parameter Description Symbol V V for Data Retention Data Retention Current DR t CE2 Setup Time CS t CE2 Hold Time CH t CE2 Pulse Width ...
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pSRAM ADDRESS SKEW CE#1 WE# Address Note: If multiple invalid address cycles shorter than t cycle over t is required during that period. RC min CE#1 WE# Address Note: If multiple invalid address ...
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PHYSICAL DIMENSIONS FLB073—73-Ball Fine-Pitch Grid Array Am49DL640BH December 5, 2003 ...
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REVISION SUMMARY Revision A (October 8, 2002) Initial release. Revision A+1 (December 5, 2003) MCP Block Diagram Corrected the common address for the Flash and pSRAM. Trademarks Copyright © 2003 Advanced Micro Devices, ...