AM49DL640BH56IS SPANSION [SPANSION], AM49DL640BH56IS Datasheet - Page 57

• Manufacturer Part Number: AM49DL640BH56IS
• Description: 64 Megabit (8 M x 8-Bit/4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory
• Manufacturer: SPANSION [SPANSION]

pSRAM AC CHARACTERISTICS
Write Cycle
Notes:
1. If the device is using the I/Os to output data, input signals of reverse polarity must not be applied.
2. If OE# is high during the write cycle, the outputs will remain at high impedance.
3. If CE#1ps, LB# or UB# goes low at the same time or after WE# goes low, the outputs will remain at high impedance.
4. If CE#1ps, LB# or UB# goes high at the same time or before WE# goes high, the outputs will remain at high impedance.
December 5, 2003
DQ15 to DQO
DQ15 to DQ0
Parameter
Symbol
Addresses
A20 to A0
t
t
t
t
LB#, UB#
t
t
t
ODW
OEW
WEH
t
t
t
t
t
t
t
CEH
WC
CW
WR
WP
BW
AW
AS
DS
DH
CH
CE#1s
D
CE2s
WE#
OUT
D
IN
Description
Write Cycle Time
Write Pulse Time
Chip Enable to End of Write
Data Byte Control to End of Write
Address Valid to End of Write
Address Setup Time
Write Recovery Time
WE# Low to Write to Output High-Z
WE# High to Write to Output Active
Data Set-up Time
Data Hold from Write Time
CE2 Hold Time
Chip Enable High Pulse Width
Write Enable High Pulse Width
(Note 1)
(Note 3)
t
CH
Figure 31. Pseudo SRAM Write Cycle—WE# Control
t
AS
A D V A N C E
t
ODW
Am49DL640BH
Max
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
t
AW
I N F O R M A T I O N
t
CW
t
BW
t
WC
t
WP
56
High-Z
Valid Data In
t
DS
70
50
60
60
60
Speed
t
OEW
t
300
DH
70
20
30
10
0
0
0
0
6
t
WR
t
WEH
(Note 4)
85
85
60
70
70
70
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
55