AM49DL640BH56IS SPANSION [SPANSION], AM49DL640BH56IS Datasheet - Page 12

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AM49DL640BH56IS

Manufacturer Part Number
AM49DL640BH56IS
Description
64 Megabit (8 M x 8-Bit/4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory
Manufacturer
SPANSION [SPANSION]
Datasheet
Legend: L = Logic Low = V
A
Notes:
1.
2. Do not apply CE#f = V
3. Don’t care or open LB#s or UB#s.
4. If WP#/ACC = V
10
Operation
(Notes 1, 2)
Read from
Flash
Write to Flash
Standby
Deep Power-down
Standby
Output Disable
Flash Hardware
Reset
Sector Protect
(Note 5)
Sector
Unprotect
(Note 5)
Temporary
Sector
Unprotect
Read from pSRAM
Write to pSRAM
IN
= Address In, D
Other operations except for those indicated in this column are
inhibited.
same time.
= V
If WP#/ACC = V
40%.
IH
the boot sectors protection will be removed.
(Note 7)
(Note 8)
(Note 7)
(Note 8)
(Note 7)
(Note 8)
(Note 7)
(Note 8)
(Note 7)
(Note 8)
(Note 7)
(Note 8)
IN
IL
ACC
= Data In, D
, the boot sectors will be protected. If WP#/ACC
(9V), the program time will be reduced by
IL
IL
, CE1#s = V
, H = Logic High = V
V
V
CE#f
0.3 V
0.3 V
Table 1. Device Bus Operations—Flash Word Mode, CIOf = V
CC
CC
X
X
H
H
L
L
L
L
L
±
±
OUT
CE1#s
= Data Out
H
H
H
H
H
H
H
H
H
H
H
H
H
H
IL
L
L
L
A D V A N C E
and CE2s = V
CE2s
IH
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
, V
ID
= 11.5–12.5 V, V
OE# WE#
IH
H
X
X
H
H
X
H
H
X
X
L
L
at the
Am49DL640BH
H
H
H
H
L
X
X
X
L
L
X
L
I N F O R M A T I O N
A1 = H, A0 = L
SADD, A6 = H,
A1 = H, A0 = L
SADD, A6 = L,
HH
Address
= 9.0 ± 0.5 V, X = Don’t Care, Byte Mode, SADD = Flash Sector Address,
A
A
A
A
X
X
X
X
X
X
IN
IN
IN
IN
5. The sector protect and sector unprotect functions may also be
6. If WP#/ACC = V
7. Data will be retained in pSRAM.
8.
implemented via programming equipment. See the “Sector/Sector
Block Protection and Unprotection” section.
protected. If WP#/ACC = V
protection depends on whether they were last protected or
unprotected using the method described in “Sector/Sector Block
Protection and Unprotection”. If WP#/ACC = V
be unprotected.
Data will be lost in pSRAM.
LB#s UB#s RESET#
H
H
X
X
X
X
X
X
X
X
X
X
L
L
L
L
X
X
X
X
X
X
X
X
X
X
H
H
L
L
L
L
IL
, the two outermost boot sectors remain
V
V
0.3 V
0.3 V
V
V
V
CC
CC
H
H
H
H
H
L
ID
ID
ID
IH
±
±
, the two outermost boot sector
WP#/ACC
IH
(Note 4)
(Note 4)
(Note 6)
(Note 6)
L/H
L/H
L/H
L/H
H
H
X
X
December 5, 2003
HH,
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
DQ7–
D
D
D
DQ0
D
D
D
D
D
D
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
all sectors will
DQ15–
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
D
D
D
DQ8
D
D
D
OUT
OUT
OUT
X
X
IN
IN
IN

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