AM49DL640BH56IS SPANSION [SPANSION], AM49DL640BH56IS Datasheet - Page 5

• Manufacturer Part Number: AM49DL640BH56IS
• Description: 64 Megabit (8 M x 8-Bit/4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory
• Manufacturer: SPANSION [SPANSION]

TABLE OF CONTENTS
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Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5
MCP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 5
Flash Memory Block Diagram. . . . . . . . . . . . . . . . 6
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9
MCP Device Bus Operations . . . . . . . . . . . . . . . . . 9
Flash Device Bus Operations . . . . . . . . . . . . . . . 12
Common Flash Memory Interface (CFI) . . . . . . . 22
Flash Command Definitions . . . . . . . . . . . . . . . . 25
December 5, 2003
Continuity of Specifications ...................................................... 1
Continuity of Ordering Part Numbers ....................................... 1
For More Information ................................................................ 1
Special Package Handling Instructions .................................... 7
Word/Byte Configuration ........................................................ 12
Requirements for Reading Array Data ................................... 12
Writing Commands/Command Sequences ............................ 12
Simultaneous Read/Write Operations with Zero Latency ....... 12
Standby Mode ........................................................................ 13
Automatic Sleep Mode ........................................................... 13
RESET#: Hardware Reset Pin ............................................... 13
Output Disable Mode .............................................................. 13
Sector/Sector Block Protection and Unprotection .................. 18
Write Protect (WP#) ................................................................ 18
Temporary Sector Unprotect .................................................. 19
SecSi™ (Secured Silicon) Sector
Flash Memory Region ............................................................ 21
Hardware Data Protection ...................................................... 21
Reading Array Data ................................................................ 25
Reset Command ..................................................................... 25
Autoselect Command Sequence ............................................ 25
Enter SecSi™ Sector/Exit SecSi Sector
Command Sequence .............................................................. 25
Byte/Word Program Command Sequence ............................. 26
Table 1. Device Bus Operations—Flash Word Mode, CIOf = V
Table 2. Device Bus Operations—Flash Byte Mode, CIOf = V
Accelerated Program Operation .......................................... 12
Autoselect Functions ........................................................... 12
Table 3. Am29DL640H Sector Architecture ....................................14
Table 4. Bank Address ....................................................................17
Table 5. SecSi™ Sector Addresses ...............................................17
Table 6. Am29DL640H Boot Sector/Sector Block Addresses for Pro-
tection/Unprotection ........................................................................18
Table 7. WP#/ACC Modes ..............................................................19
Figure 1. Temporary Sector Unprotect Operation........................... 19
Figure 2. In-System Sector Protect/Unprotect Algorithms .............. 21
Low V
Write Pulse “Glitch” Protection ............................................ 22
Logical Inhibit ...................................................................... 22
Power-Up Write Inhibit ......................................................... 22
Table 8. CFI Query Identification String .......................................... 22
System Interface String................................................................... 23
Table 10. Device Geometry Definition ............................................ 23
Table 11. Primary Vendor-Specific Extended Query ...................... 24
Unlock Bypass Command Sequence .................................. 26
CC
Write Inhibit .......................................................... 22
A D V A N C E
IL
Am49DL640BH
IH
.... 11
... 10
I N F O R M A T I O N
Flash Write Operation Status . . . . . . . . . . . . . . . 30
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 34
ESD IMMUNITY . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Flash DC Characteristics . . . . . . . . . . . . . . . . . . 35
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 38
pSRAM AC Characteristics . . . . . . . . . . . . . . . . . 39
Chip Erase Command Sequence ........................................... 27
Sector Erase Command Sequence ........................................ 27
Erase Suspend/Erase Resume Commands ........................... 28
DQ7: Data# Polling ................................................................. 30
RY/BY#: Ready/Busy# ............................................................ 31
DQ6: Toggle Bit I .................................................................... 31
DQ2: Toggle Bit II ................................................................... 32
Reading Toggle Bits DQ6/DQ2 ............................................... 32
DQ5: Exceeded Timing Limits ................................................ 32
DQ3: Sector Erase Timer ....................................................... 32
CMOS Compatible .................................................................. 35
pSRAM DC & Operating Characteristics ................................ 36
CE#s Timing ........................................................................... 39
Read-Only Operations ........................................................... 40
Hardware Reset (RESET#) .................................................... 41
Word/Byte Configuration (CIOf) .............................................. 42
Erase and Program Operations .............................................. 43
Temporary Sector Unprotect .................................................. 48
Alternate CE#f Controlled Erase and Program Operations .... 50
Read Cycle ............................................................................. 52
Figure 3. Program Operation ......................................................... 27
Figure 4. Erase Operation.............................................................. 28
Table 12. Am29DL640H Command Definitions .............................. 29
Figure 5. Data# Polling Algorithm .................................................. 30
Figure 6. Toggle Bit Algorithm........................................................ 31
Table 13. Write Operation Status ................................................... 33
Figure 7. Maximum Negative Overshoot Waveform ...................... 34
Figure 8. Maximum Positive Overshoot Waveform........................ 34
Figure 9. I
Automatic Sleep Currents) ............................................................. 37
Figure 10. Typical I
Figure 11. Test Setup.................................................................... 38
Figure 12. Input Waveforms and Measurement Levels ................. 38
Figure 13. Timing Diagram for Alternating
Between Pseudo SRAM to Flash................................................... 39
Figure 14. Read Operation Timings ............................................... 40
Figure 15. Reset Timings ............................................................... 41
Figure 16. CIOf Timings for Read Operations................................ 42
Figure 17. CIOf Timings for Write Operations................................ 42
Figure 18. Program Operation Timings.......................................... 44
Figure 19. Accelerated Program Timing Diagram.......................... 44
Figure 20. Chip/Sector Erase Operation Timings .......................... 45
Figure 21. Back-to-back Read/Write Cycle Timings ...................... 46
Figure 22. Data# Polling Timings (During Embedded Algorithms). 46
Figure 23. Toggle Bit Timings (During Embedded Algorithms)...... 47
Figure 24. DQ2 vs. DQ6................................................................. 47
Figure 25. Temporary Sector Unprotect Timing Diagram .............. 48
Figure 26. Sector/Sector Block Protect and
Unprotect Timing Diagram ............................................................. 49
Figure 27. Flash Alternate CE#f Controlled Write (Erase/Program)
Operation Timings.......................................................................... 51
Figure 28. Psuedo SRAM Read Cycle........................................... 52
Figure 29. Page Read Timing ........................................................ 53
CC1
Current vs. Time (Showing Active and
CC1
vs. Frequency ........................................... 37
3