IC42S16100-5T ICSI [Integrated Circuit Solution Inc], IC42S16100-5T Datasheet - Page 47
![no-image](/images/no-image-200.jpg)
IC42S16100-5T
Manufacturer Part Number
IC42S16100-5T
Description
512K x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM
Manufacturer
ICSI [Integrated Circuit Solution Inc]
Datasheet
1.IC42S16100-5T.pdf
(78 pages)
- Current page: 47 of 78
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IC42S16100
Write Cycle / Ping-Pong Operation
Integrated Circuit Solution Inc.
DR024-0D 06/25/2004
Note 1: A8,A9 = Don't Care.
A0-A9
CAS latency = 2, burst length = 2
DQM
CKE
RAS
CAS
CLK
A10
A11
WE
CS
I/O
t
CKS
t
CS
T0
t
t
t
t
t
t
t
CS
t
t
CS
CS
AS
AS
AS
CKA
CK
CH
<
BANK 0
ACT 0
ROW
ROW
T1
(BANK 0 TO 1)
t
CHI
>
(BANK 0)
(BANK 0)
(BANK 0)
t
t
t
t
t
RCD
t
t
RRD
t
t
RAS
t
AH
AH
CH
CH
CH
RC
AH
T2
t
CL
t
t
DS
CS
<
AUTO PRE
<
WRITA 0
COLUMN
NO PRE
WRIT 0
BANK 0
D
T3
IN
0m
t
(1)
DH
>
>
t
DS
<
BANK 1
ACT 1
ROW
ROW
D
T4
IN
0m+1
t
>
DH
(BANK 1)
(BANK 1)
(BANK 1)
t
t
RCD
RAS
t
RC
t
DS
D
T5
IN
0m+2
t
DH
t
DS
D
T6
IN
0m+3
t
DH
t
DPL
t
DS
<
AUTO PRE
<
NO PRE
WRITA 1
COLUMN
WRIT 1
BANK 1
T7
D
IN
t
1m
DH
(1)
>
>
t
DS
BANK 0 OR 1
<
BANK 0
PRE 0
D
T8
IN
1m+1
t
DH
>
(BANK 0)
t
RP
t
DS
D
T9
IN
1m+2
t
DH
t
DS
T10
<
BANK 0
ACT 0
D
ROW
ROW
IN
1m+3
Undefined
Don’t Care
t
>
DH
(BANK 0)
(BANK 0)
(BANK 0)
t
t
t
RCD
RAS
t
DPL
RC
t
CH
47
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