IC42S16100-5T ICSI [Integrated Circuit Solution Inc], IC42S16100-5T Datasheet - Page 54
![no-image](/images/no-image-200.jpg)
IC42S16100-5T
Manufacturer Part Number
IC42S16100-5T
Description
512K x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM
Manufacturer
ICSI [Integrated Circuit Solution Inc]
Datasheet
1.IC42S16100-5T.pdf
(78 pages)
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IC42S16100
Read Cycle / Precharge Termination
54
A0-A9
Note 1: A8,A9 = Don't Care.
DQM
CAS latency = 2, burst length = 4
CKE
RAS
CAS
CLK
A10
A11
WE
CS
I/O
t
CKS
t
CS
T0
t
t
t
t
t
t
t
CS
CS
CS
AS
AS
t
t
AS
CKA
CH
CK
BANK 0
<
ROW
ROW
ACT 0
T1
t
CHI
>
t
t
t
t
t
t
t
t
t
RCD
RAS
RC
AH
AH
CH
CH
CH
AH
T2
t
CL
t
CS
<
COLUMN m
NO PRE
READ 0
BANK 0
T3
(1)
>
t
t
CAC
QMD
t
LZ
T4
t
AC
T5
D
OUT
t
OH
m
t
AC
t
CH
BANK 0 OR 1
<
BANK 0
PRE 0
T6
D
OUT
>
t
OH
m+1
t
t
AC
RQL
t
RP
T7
D
OUT
t
OH
m+2
t
HZ
<
BANK 0
BANK 1
ACT
Integrated Circuit Solution Inc.
ROW
ROW
T8
>
t
t
t
RAS
RCD
RC
T9
DR024-0D 06/25/2004
AUTO PRE
COLUMN n
<
NO PRE
BANK 1
BANK 0
<
T10
READA
READ
>
Undefined
Don’t Care
(1)
>
t
CAC
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