MT54W1MH36B-4 MICRON [Micron Technology], MT54W1MH36B-4 Datasheet - Page 11

• Manufacturer Part Number: MT54W1MH36B-4
• Manufacturer: MICRON [Micron Technology]

NOTE:
36Mb: 1.8V V
MT54W2MH18B_A.fm - Rev 9/02
1. The address is concatenated with one additional internal LSB to facilitate burst operation. The address order is always fixed as xxx .
2. State transitions: RD = (R# = LOW); WT = (W# = LOW).
3. Read and write state machines can be simultaneously active.
4. State machine control timing sequence is controlled by K.
. . xxx + 0, xxx . . . xxx + 1. Bus cycle is terminated at the end of this sequence (burst count = 2).
DD
WRITE ADDRESS
READ ADDRESS
, HSTL, QDRIIb2 SRAM
LOAD NEW
LOAD NEW
AT K#
always
always
RD
WT
4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36
Bus Cycle State Diagram
WRITE DOUBLE
READ DOUBLE
WT
RD
Figure 4
AT K#
11
1.8V V
Micron Technology, Inc., reserves the right to change products or specifications without notice.
/RD
/WT
DD
, HSTL, QDRIIb2 SRAM
WRITE PORT NOP
READ PORT NOP
POWER-UP
R_Init=0
Supply voltage
Supply voltage
provided
provided
©2002, Micron Technology Inc.
ADVANCE
/RD
/WT