MT54W1MH36B-4 MICRON [Micron Technology], MT54W1MH36B-4 Datasheet - Page 16

• Manufacturer Part Number: MT54W1MH36B-4
• Manufacturer: MICRON [Micron Technology]

AC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING
CONDITIONS
0ºC £ T
NOTE:
36Mb: 1.8V V
MT54W2MH18B_A.fm - Rev 9/02
1. Test conditions as specified with the output loading shown in Figure 5, unless otherwise noted.
2. Control input signals may not be operated with pulse widths less than
3. If C and C# are tied HIGH, K and K# become the references for C and C# timing parameters.
4. The device will operate at clock frequencies slower than
5. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
6. V
7. Echo clock is tightly controlled to data valid/data hold. By design, there is a ±0.1ns variation from echo clock to data. The data sheet
8. This is a syncrhonous device. All addresses, data, and control lines must meet the specified setup and hold times for all latching clock
DESCRIPTION
Hold Times
K rising edge to address
hold
K rising edge to control
inputs hold
K, K# rising edge to data-in
hold
parameters reflect tester guardbands and test setup variations.
edges.
DD
8
8
A
slew rate must be less than 0.1V DC per 50ns for DLL lock retention. DLL lock time begins once V
DD
£ +70ºC;
, HSTL, QDRIIb2 SRAM
8
+1.7V £ V
1, 2, 3, 6, 8
DD
£ +1.9V
SYMBOL
t
t
t
KHAX
KHDX
KHIX
4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36
MIN
0.40
0.40
0.40
-4
t
MAX
KHKH (MAX). See Micron Technical Note TN-54-02 for more information.
16
MIN
0.50
0.50
0.50
t
KHKL (MIN).
1.8V V
-5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MAX
DD
0.60
0.70
0.60
MIN
, HSTL, QDRIIb2 SRAM
-6
MAX
DD
and input clock are stable.
0.70
0.70
0.70
MIN
-7.5
©2002, Micron Technology Inc.
MAX
ADVANCE
UNITS
ns
ns
ns