SCD1283 INTEL [Intel Corporation], SCD1283 Datasheet - Page 3

• Manufacturer Part Number: SCD1283
• Description: IEEE 1284-Compatible Parallel Interface
• Manufacturer: INTEL [Intel Corporation]

Contents
1.0
2.0
3.0
4.0
5.0
Datasheet
Overview
1.1
Conventions
Pin Information
3.1
3.2
3.3
Register Summary
4.1
Functional Description
5.1
5.2
5.3
5.4
5.5
5.6
Advantages ........................................................................................................... 9
Pin Diagram.........................................................................................................13
Pin List.................................................................................................................14
Pin Descriptions ..................................................................................................16
Register Summary Tables...................................................................................19
Device Architecture .............................................................................................22
CPU Interface......................................................................................................22
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
5.2.6
5.2.7
Parallel Port Service Requests............................................................................27
5.3.1
5.3.2
Parallel Port FIFO and Data Pipeline ..................................................................32
5.4.1
5.4.2
5.4.3
5.4.4
5.4.5
5.4.6
5.4.7
Parallel Port Overview.........................................................................................36
5.5.1
5.5.2
5.5.3
5.5.4
5.5.5
5.5.6
5.5.7
5.5.8
5.5.9
5.5.10 Data Transfers........................................................................................40
5.5.11 Compatibility Mode Status......................................................................40
IEEE 1284 Parallel Protocol Support ..................................................................40
........................................................................................................................ 9
Read Cycles ...........................................................................................24
Write Cycles ...........................................................................................24
Service-Acknowledge Cycles .................................................................24
DMA Cycles............................................................................................24
Interrupts ................................................................................................25
DMAREQ* as Interrupt Source...............................................................25
Daisy-Chain Configurations....................................................................26
Hardware-Activated Acknowledge .........................................................32
Software-Activated Acknowledge...........................................................32
IEEE Standard 1284 Protocols...............................................................33
Bus Interface ..........................................................................................33
Parallel Port FIFO...................................................................................34
Receive Direction ...................................................................................34
Receiving Compressed Data..................................................................35
Stale Data (Stale, OneChar, and Timeout Status Bits) ..........................35
Transmit Direction ..................................................................................36
Terminology............................................................................................36
Signal Names .........................................................................................37
State Machine ........................................................................................37
Configuration ..........................................................................................37
Interrupts ................................................................................................37
Manual Mode..........................................................................................38
Control Signals .......................................................................................38
Parallel Port Interface to the FIFO..........................................................39
IEEE 1284-Protocol Negotiations...........................................................39
...............................................................................................................11
..........................................................................................................13
...................................................................................................19
...........................................................................................22
IEEE 1284-Compatible Parallel Interface — CD1283
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