SCD1283 INTEL [Intel Corporation], SCD1283 Datasheet - Page 49

• Manufacturer Part Number: SCD1283
• Description: IEEE 1284-Compatible Parallel Interface
• Manufacturer: INTEL [Intel Corporation]

6.2.2
Datasheet
The following section of programming code shows a typical initialization sequence preparing the
parallel channel for Compatibility mode data reception and enabling negotiation into all modes,
except EPP. This procedure can also be used as part of a diagnostic test suite. The device will
complete internal initialization within 500 sec. Therefore, a timer (software or hardware) can be
used to detect that the operation does not complete within this time and that the device may not be
functional.
/* Initialization of the parallel channel consists of setting the SPR, selecting
modes that will be supported during negotiation, stale data timeout value,
initalizing the FIFO, the source for interrupts that will be accepted and other
operational functions. */
par_init()
{
signals: */
Write */
input, */
reset*/
starting */
32) */
}
Service Acknowledge Handling
Service request and acknowledge processing, as well as DMA request and acknowledge
processing, is performed by the internal MPU. It is important to take the behavior of the MPU into
account if interrupts are used. There are two different variations where service requests can be
serviced. One variation uses the SVCACKP*, the other does not. If the SVCACKP* signal is
activated through an input instruction then the device will return the value of the LIVR on the data
bus. This can be used as a vector to the service routine or used in a switch instruction to jump to the
correct routine.
/* First, issue chip reset command */
outportb(GFRCR, 0x00);
outportb(AER, 0x02);
while (inportb(RCR) != 0x00)
outportb(RCR, 0x81);
while (inportb(GFRCR) != 0x00);/* Wait for GFRCR to be cleaared */
while (inportb(GFRCR) != 0x25);/* Wait for GFRCR to be set */
/* Start by initializing the parallel channel */
outportb(AER, 0x00);
outportb(SPR, 0x0d);
outportb(NER, 0x4f);
outportb(OVR, 0x18);
outportb(PCIER, 0x37);
outportb(PCR, 0x60);
/* Next, set up the pipeline control registers */
outportb(LIVR, 0x00);
outportb(PFCR, 0xd8);
outportb(PFCR, 0x58);
outportb(PFTR, 0x20);
outportb(SDTPR, 0x64);
outportb(PACR, 0x02);
;
IEEE 1284-Compatible Parallel Interface — CD1283
/* Clear the GFRCR */
/* AER must equal 02h or o3h to access RCR*/
/* Wait for RCR to clear */
/* Set the Access Enable Register */
/* Assume 25MHz clock, set short pulse value */
/* Support all modes except EPP */
/* Start in Compatibility mode, set status
/*
/* Enable all interrupts except EPP Address
/* Enable 1284 negotiations and transfers */
/* Initialize the interrupt vector to 0 */
/* Enable pipeline DMA, set the direction to
/* enable interrupts (but not error ints) and
/* the FIFO. At reset, it is assumed that the
/* direction will be input. */
/* Remove Reset */
/* Set the DMA threshold for receive (burst =
/* Set the stale data timeout period to 10ms */
/* Set asynchronous DMA mode */
PError = 0 */
/* SELCT = 1 */
/* nFault = 1 */
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