SCD1283 INTEL [Intel Corporation], SCD1283 Datasheet - Page 74

• Manufacturer Part Number: SCD1283
• Description: IEEE 1284-Compatible Parallel Interface
• Manufacturer: INTEL [Intel Corporation]

CD1283 — IEEE 1284-Compatible Parallel Interface
7.4.13
7.4.14
7.5
7.5.1
74
Register Name: SSR
Register Description: Signal Status
Access: R/W
Register Name: ZDR
Register Description: Zero Detect
Access: R/W
Register Name: RCR
Register Description: Reset Command
Access: R/W
Table 11. SPR Binary Values to Set 500-ns Pulse Widths
Bit 7
Bit 7
Bit 7
0
0
1
Signal Status Register
The bits in this register show the results of changes specified in the ODR and ZDR. Normally, the
host will read this register in response to a signal-change interrupt generated by the CD1283. SSR
is active and valid only in Manual mode. Bits 7:4 return zeros when read. A write of any value to
SSR clears it.
Zeros Detect Register
When the bits 3:0 in ZDR are set, it enables the CD1283 to generate an interrupt (if the SigCh bit in
PCIER is set) when the selected signal changes from high-to-low (falling edge). Bits 7:4 are
reserved and must be written as ‘0’; these bits return ‘0’ when read. This register is enabled only
during Manual mode.
Special Register
Reset Command Register
Bit 6
Bit 6
Bit 6
0
0
0
Clock
(MHz)
16
20
25
Bit 5
Bit 5
Bit 5
SPR Value
0
0
0
10
13
8
Bit 4
Bit 4
Bit 4
0
0
0
Resultant Pulse Width
(ns)
A1284
500
500
520
A1284
Bit 3
Bit 3
Bit 3
0
Bit 2
nInit
Bit 2
Bit 2
nInit
0
HstBsy
HstBsy
Bit 1
Bit 1
Bit 1
8-Bit Hex Address: 2C
8-Bit Hex Address: 2F
8-Bit Hex Address: 05
0
Default Value: 00
Default Value: 00
Default Value: 00
Datasheet
HstClk
HstClk
Bit 0
Bit 0
Bit 0
1