SCD1283 INTEL [Intel Corporation], SCD1283 Datasheet - Page 57

• Manufacturer Part Number: SCD1283
• Description: IEEE 1284-Compatible Parallel Interface
• Manufacturer: INTEL [Intel Corporation]

7.3
7.3.1
Datasheet
Register Name: DER
Register Description: Data Error
Access: Read only
DMAwrerr
Table 10. PIVR[2:0] Encoding
Bit
Bit 7
7
6
5
4
3
2
1
0
IT2
0
•
0
1
1
1
1
DMA Write Error: This bit is set if the DMA control logic has written to the DMA buffer when it already contains
data. It indicates that an invalid DMA transfer cycle occurred (a DMAACK* without a corresponding DMAREQ*).
DMA Read Error: As with bit 7, this bit indicates that DMA logic has performed a read from the DMA Buffer when
there was no data in it. It indicates that an invalid DMA transfer cycle occurred.
Buffer Write Error: This bit indicates that a system write to the DMA buffer occurred while it still contained data.
Buffer Read Error: This bit indicates that a system read from the DMA buffer occurred while it was empty.
Holding Register 1 Write Error: This bit indicates that a system write to PFHR1 (Parallel FIFO Hold-
ing register 1) occurred while it still contained data.
Holding Register 1 Read Error: This bit indicates that a system read from PFHR1 occurred while it was empty.
Holding Register 2 Write Error: This bit indicates that a system write to PFHR2 (Parallel FIFO Holding register 2)
occurred while it still contained data.
Holding Register 2 Read Error: This bit indicates that a system read from PFHR2 occurred while it was empty.
Parallel Pipeline Registers
Data Error Register
The bits in this read-only register indicate read/write errors involving the DMA Buffer register and
the Data Pipeline registers. The DataErr bit in PFSR is the logical OR of these eight Error Status
bits.
A read of this register has no effect on the error status. A write to this register clears all bits; they
are not individually writable by the user. Host software should clear this register (write x’00) after
completing an error service-acknowledge procedure. This bit is provided primarily as an aid to
driver software development. Under normal circumstances, data errors should never occur. This
register is cleared during device reset.
DMArderr
Bit 6
IT1
0
•
1
0
0
1
1
Bufwrerr
Bit 5
IT0
1
•
1
0
1
0
1
Description
Invalid.
The parallel channel state machine requests service.
The parallel channel data pipeline requests service.
Both the parallel port state machine and the parallel port data pipeline
request service.
Invalid.
Bufrderr
Bit 4
IEEE 1284-Compatible Parallel Interface — CD1283
Description
HR1wrerr
Bit 3
HR1rderr
Bit 2
HR2wrerr
Bit 1
8-Bit Hex Address: 33
Default Value: 00
HR2rderr
Bit 0
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