SCD1283 INTEL [Intel Corporation], SCD1283 Datasheet - Page 77

• Manufacturer Part Number: SCD1283
• Description: IEEE 1284-Compatible Parallel Interface
• Manufacturer: INTEL [Intel Corporation]

Datasheet
NOTES:
1. V
2. V
multiple pull-up resistors that increase the load on the output.
C
IH
OL
C
I
I
I
OC
OUT
CC
LL
IN
is 2.7 V minimum on RESET* and CLK.
for open-drain signals is 0.5 V @ 8 mA sinking because these signals can be wire-OR’ed in some systems and can have
Note: While the CD1283 is a highly dependable device, there are a few guidelines to ensure that the
Data bus tristate leakage current
Open-drain output leakage current
Power supply current
Input capacitance
Output capacitance
The signals specific to the parallel port meet all requirements of the IEEE STD 1284 specification,
except for input signal protection ( 2.0 to
specification.
maximum possible level of overall system reliability is achieved. First, design the PC board to
provide maximum isolation of noise. A four-layer board is preferable, but a two-layer board will
work if proper power and ground distribution is implemented. In either case, decoupling capacitors
mounted close to the CD1283 are strongly recommended. Noise typically occurs when either the
CD1283 data bus drivers come out of tristate to drive the bus during a read, or when an external bus
buffer turns on during a write cycle. This noise, a rapid rate-of-change of supply current, causes
‘ground bounce’ in the power-distribution traces. This ground bounce, a rise in the voltage of the
ground pins, effectively raises the input logic thresholds of all devices in the vicinity, resulting in
the possibility of a ‘1’ being interpreted as a ‘0’.
To reduce the possibility of ground-bounce affecting the operation of the CD1283, Intel has
specified the input-high voltage (V
standard 2.0 V. This eliminates any sensitivity to ground bounce, even in extremely noisy systems.
Although 2.7 V is higher than the industry-standard 2.4-V output (V
are several simple ways to meet this specification:
Symmetrical input/output drive: 14 mA
Controlled voltage slew rate: 0.4 V/ s
Input hysteresis: 0.8 V
1. Use any of the available advanced-CMOS logic families (FACT, ACL, and so on). These
2. As noted in the Texas Instruments ALS/AS Logic Data Book (1986 — pages 4-18 and 4-19),
CMOS output buffers will pull-up close to V
ALS TTL can be used if the output of the TTL device is only driving one or two CMOS loads.
the V
publish similar data. Intel recommends the use of one of these two options for the CLK input
to ensure fast, clean edges.
Note that RESET* can, if desired, be pulled up passively with 1-k resistor.
OH
output of these families exceeds 3.0 V at low-current loading. Other manufacturers
IH
) of the CLK and RESET* pins at 2.7 V, instead of the TTL-
IEEE 1284-Compatible Parallel Interface — CD1283
10
10
7.0 V); external circuitry is required to meet this
CC
when not heavily loaded. In addition, AS and
10
10
50
10
10
OH
mA
pF
pF
A
A
) specified for TTL, there
0
0
CLK
V
OUT
V
OUT
25 MHz
V
V
CC
CC
77