HI-6121PQMF HOLTIC [Holt Integrated Circuits], HI-6121PQMF Datasheet - Page 106
HI-6121PQMF
Manufacturer Part Number
HI-6121PQMF
Description
MIL-STD-1553 Remote Terminal ICs
Manufacturer
HOLTIC [Holt Integrated Circuits]
Datasheet
1.HI-6121PQMF.pdf
(116 pages)
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VDD = 3.3 V, GND = 0V, T = Operating Temperature Range (unless otherwise specified).
HI-6120 INTERFACE TIMING (Parallel Host Bus Interface)
showing a one-word write cycle. Successive writes to sequential addresses have same timing.
A0 LB
A15:1
WAIT
D7:0
WE
CS
OE
PARAMETER
A
using BTYPE = 1 (”Intel Style” -
using BTYPE = 1 (”Intel Style” -
FIGURE 21. Register and RAM Write Operations for BTYPE = 1
HOST WRITE IN DUAL-BYTE MODE (8-BIT BUS WIDTH)
D15:0
A15:1
WAIT
HOST WRITE IN WORD MODE (16-BIT BUS WIDTH)
WE
OE
CS
All timing intervals equal
showing 2 bytes written for a single 16-bit word
16-bit sequential read time
BYTE 0
Non-sequential read time
8-bit sequential read time
t
Read/Write inactive time
WR
HOLT INTEGRATED CIRCUITS
Wait assertion time
HI-6120, HI-6121
Clock period
Write cycle
Wait time
ADDRESS
t
OE
OE
0 ns MIN
INACT
ADDRESS
WORD
t
WR
106
Output Enable and
Output Enable and
unless otherwise indicated.
SYMBOL
t
t
INACT
t
t
t
t
BYTE 1
t
SR16
WAS
CYC
NSR
SR8
WR
t
W
t
WR
t
INACT
WE
WE
MIN
110
Write Enable)
Write Enable)
80
55
25
55
65
20
t
INACT
LIMITS
OE
assertion
for the next
Read or Write
TYP
or
WE
MAX
130
OE
assertion
for the next
Read or Write
or
UNITS
WE
ns
ns
ns
ns
ns
ns
ns
ns
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