HI-6121PQMF HOLTIC [Holt Integrated Circuits], HI-6121PQMF Datasheet - Page 38

• Manufacturer Part Number: HI-6121PQMF
• Description: MIL-STD-1553 Remote Terminal ICs
• Manufacturer: HOLTIC [Holt Integrated Circuits]

DESCRIPTOR TABLE, Cont.
12
11
10
9
8
7-4
3
2
MKBUSY
DBAC
DPB
BCAST
PPON
CIR2ZN
STOPP
PPEN
Make Busy.
The host asserts the MKBUSY bit to respond with Busy status for commands to this receive
subaddress. This bit is an alternative to globally applying Busy status for all valid commands, enabled
from the 1553 Status Bits Register. See that register description for additional information. When
Busy is asserted, received data words are not stored
completion.
Descriptor Block Accessed.
Internal device logic asserts the DBAC bit upon completion of message processing. The host may
poll this bit to detect subaddress activity, instead of using host interrupts. This bit is reset to logic 0 by
MR
Data Pointer B.
This status bit is maintained by the device and only applies in ping-pong buffer mode. This bit
indicates the buffer to be used for the next occurring receive command to this subaddress. When the
DPB bit is logic 0, the next message will use Data Pointer A; when DPB is logic 1, the next message
uses Data Pointer B. In ping-pong buffer mode, the bit is inverted after each
completion. The DPB bit is not altered after messages ending in error, after illegal commands or after
messages when the terminal responds with Busy status. This bit is reset to logic 0 by
or SRST software reset; therefore the first message received after either reset will use Buffer A. This
bit is “don’t care” for indexed single-buffer mode or either circular buffer mode.
Broadcast Command.
Device logic sets this bit when a valid broadcast receive command is received at this subaddress. If
IBRD bit 13 and Interrupt Enable Register IBRD bit are both set, the output pin
This bit has no function if the BCSTINV bit is asserted in the Configuration Register 1; in this case
commands to RT address 31 are not recognized as valid by the device.
MR
Ping-Pong Enable Acknowledge.
This bit is controlled by the device and cannot be written by the host. It only applies if PPEN bit 2 was
initialized to logic one by the host after reset, enabling ping-pong buffer mode for this subaddress.
Device logic asserts this bit when it recognizes ping-pong is active for this subaddress. Before off-
loading the receive data buffer for this subaddress, the host can ask the device to temporarily disable
ping-pong by asserting STOPP bit 3. The device acknowledges ping-pong is disabled by negating
PPON. The host can safely off-load the buffer without data collision while PPON is negated. After
buffer servicing, the host asks the device to re-enable ping-pong by negating STOPP bit 3. The
device acknowledges ping-pong is re-enabled by asserting PPON.
If PPEN bit 2 is high and PPON bit 8 is low when new commands arrive for this subaddress, ping-
pong is disabled. Each new message overwrites existing data in the buffer specified by DPB bit 10,
and the DPB bit does not toggle after command completion.
Circular Mode 2 Zero Number.
Used only in circular buffer mode 2, this 4-bit field is initialized with the number of trailing zeros in the
initialized MIBA address. This is explained in a later section that fully describes circular buffer mode 2.
Stop Ping-Pong Request.
The host asserts this bit to suspend ping-pong buffering for this subaddress. The host resets this bit to
ask the device to re-enable ping-pong. The device confirms recognition of ping-pong enable or
disable status by writing PPON bit 8. Refer to later section fully describing ping-pong mode.
Ping-Pong Buffer Enable.
The PPEN, CIR1EN and CIR2EN bits are initialized by the host to select buffer mode. For
explanation, see description below for bits 1-0.
After reset, the host initializes the PPEN bit to logic one to enable ping-pong buffering for this
subaddress. The host asserts STOPP bit 3 to ask the device to temporarily disable ping-pong.
Negating the STOPP bit asks the device to re-enable ping-pong. The device confirms ping-pong
enable or disable state changes by writing the PPON bit.
master reset, SRST software reset or a host read cycle to this memory address.
master reset or SRST software reset.
HOLT INTEGRATED CIRCUITS
HI-6120, HI-6121
38
and the DPB bit does not toggle after message
This bit is reset to logic 0 by
INTMES
error-free
MR
master reset
is asserted.
message