HI-6121PQMF HOLTIC [Holt Integrated Circuits], HI-6121PQMF Datasheet - Page 75

• Manufacturer Part Number: HI-6121PQMF
• Description: MIL-STD-1553 Remote Terminal ICs
• Manufacturer: HOLTIC [Holt Integrated Circuits]

RESET AND INITIALIZATION, Cont.
HOST BUS INTERFACE (HI-6120 ONLY)
I
16 address space. The lowest 32 addresses access
registers and the remaining addresses access RAM
locations.
The HI-6120 uses a parallel bus interface for
communications with the host. Host interface to registers
and RAM is enabled through the Chip Enable (
accessed via 16-bit data bus and several host-originated
control signals described below.
register operations and RAM operations via the host bus
interface, but read and write operations have different
signal timing. The HI-6120 parallel host bus interface is
capable of faster communication than the HI-6121 Serial
Peripheral Interface.
Depending on the chosen microprocessor family, the
processor’s
an “external bus interface,” “memory interface” or may
have a different name. The user can also implement a
software controlled “bit-banged” interface to the HI-6120,
at the cost of substantially slower RAM and register
read/write times.
The bus interface is compatible with the two prevalent bus
control signal methods: “Intel style” interface,
characterized by separate strobes for read and write
operations (
characterized by a single read/write strobe (
data direction signal (R/ ). Bus control style is selected
using the BTYPE configuration pin, which sets the function
of two other input pins to serve as either
STR
The BWID configuration pin selects either 8- or 16-bit bus
widths. When the BWID pin is connected to ground, 8-bit
mode is selected; two bytes are sequentially transferred
for each 16-bit word operation. In 8-bit mode only, the
BENDI configuration pin selects bus “endianness.” This
the system attribute that indicates whether integers are
represented with the most significant byte stored at the
lowest address (big endian) or at the highest address (little
endian). Internal device storage is “big endian”. For
processor compatibility, the BENDI pin sets the order for
byte accesses when the host bus is configured for 8-bit
width, that is, when BWID equals 0. When BENDI is low,
n the HI-6120, internal RAM and registers occupy a 32K x
from device registers and RAM to EEPROM. This
range covers all registers, all configuration tables in
RAM, the primary Descriptor Table in RAM at address
0x0200 to 0x03FF. As long as EE1K remains low when
auto-initialization occurs, the 32K x 16 programming
option can initialize secondary Descriptor Tables
above address 0x0400, if used. The 32K x 16 write to
EEPROM requires up to 1.9 seconds.
and R/ .
W
OE
hardware bus interface
and
WE
W
), and “Motorola style” interface,
Timing is identical for
may be described as
OE
HOLT INTEGRATED CIRCUITS
CE
STR
and
) pin, and
) and a
HI-6120, HI-6121
WE
, or
is
75
The 32K x 16 programming option (EE1K equals zero) can
also initialize fixed data for any subset of the 32 possible
transmit subaddress buffers, using any of the defined data
buffer schemes. To enable EEPROM copy for transmit
subaddress data buffers, the buffer space must be pre-
loaded with the desired data. Be sure to reserve space for
Message Information and Time-Tag Word locations, as
required for the transmit subaddress buffer method.
“little endian” is chosen; the low order byte (bits 7:0) is
transacted before the high order byte (bits 15:8). When
BENDI is high, “big endian” is chosen and the high order
byte is transacted on the host bus before the low order
byte. In 8-bit mode, all transacted data uses bus data bits
7:0 and bus data bits 15:8 are not used. Further, bus
address bit A0 (
read/write access, and equals 1 during the second byte
access
When the BWID pin is connected high or left unconnected,
16-bit bus width is used. For 16-bit bus operation, the A0
(
“don’t care.”
A WAIT output pin can be used to modify host timing for bus
read cycles. For
processors, the WAIT output can be made active high or
active low, set by the state of the WPOL input pin. The
WAIT output may be ignored when the host processor’s
read and write cycle times are consistent with worst case
(slowest) read/write cycle timing for this device. The WAIT
output is useful when the host processor runs at high clock
rates and/or when processor options for read wait states
do not provide adequate timing margin with worst case
(slowest) read/write timing for this device. The WAIT is not
used for write operations.
WAIT is always asserted during the first read cycle. This
may be the first byte read in 8-bit mode, or the first word
read in 16-bit mode, possibly the first word read from a
series of sequential addresses. After each word (or byte)
is fetched by the device for a read operation, the next word
(or byte) is pre-fetched from the next address to speed-up
the read cycle time when immediate, sequential read to the
next address occurs. For fastest read access under all
conditions, the user can set host processor bus timing to
match the faster rate for the second and subsequent read
cycles, while using the WAIT output to pace access for the
slower initial read cycle.
Timing diagrams for bus read and write operations are
shown in the AC Electrical Characteristics section of the
datasheet.
“Motorola style” control interfaces.
LB
) address pin is not used and the BENDI input pin is
Separate diagrams show
LB
) always equals 0 during the first byte
compatibility with different host
“Intel style” and