HI-6121PQMF HOLTIC [Holt Integrated Circuits], HI-6121PQMF Datasheet - Page 21

• Manufacturer Part Number: HI-6121PQMF
• Description: MIL-STD-1553 Remote Terminal ICs
• Manufacturer: HOLTIC [Holt Integrated Circuits]

REGISTERS, Cont.
7
6-5
4
3
2
1
0
The Interrupt Enable Register lets the host temporarily or permanently disable interrupt servicing for some or all interrupt
types.
Asserting a bit in the Interrupt Enable register after an event occurs does not generate an interrupt for that event.
IWA and IBR interrupts result from message processing. The host can enable or disable these three interrupt types for
individual subaddresses and mode code commands by setting or resetting the IXEQZ, IWA and IBR bits in d
Control Words corresponding to each subaddress or mode command. While the ILCMD and MERR interrupts also result from
message processing, these interrupts (along with all hardware interrupts) are globally enabled or disabled, and are unaffected
by descriptor table settings. Here is a summary of settings and responses to interrupt-causing messages:
Descriptor Control Word Interrupt Enable Register
IXEQZ, IWA & IBR bits
All Interrupts Except
(no Control Word bits)
IXEQZ, IWA and IBR
When bits are reset in this register, interrupt output signals are globally disabled for the corresponding interrupt types.
LBFA, LBFB Loopback Fail Bus A and Loopback Fail Bus B Interrupts.
RTAPF
RAMIF
TTINT1
TTINT0
EECKF
SPIFAIL
Reset
Set
Set
Time-Tag Interrupt 1.
Time-Tag Interrupt 0.
Initialization EEPROM Checksum Fail Interrupt.
applied. When illegal commands are received, the terminal responds by transmitting status word with
ME “message error” flag set; no data words are transmitted. If this ILCMD bit is high, all illegal
commands cause
Register” (below) and the section entitled “Illegalization Table” for further information.
SPI Fail Interrupt (HI-6121 only).
The HI-6121 uses a SPI interface for host access. The device operates in SPI Slave mode. When
this bit is high, the
number of SCK clocks occurs during SPI chip select assertion.
During all transmitted command responses, the device compares words transmitted to the received
and decoded words detected on the bus. When this bit is high, the
Interrupt Log is updated each time loopback detects word mismatch.
If this bit is logic 1, the
Interrupt register each time the free-running Time-Tag counter value matches the value stored in the
Time-Tag Utility Register.
If this bit is logic 1, the
Interrupt register each time the free-running Time-Tag counter value rolls over from 0xFFFF full count
to 0x0000.
RTAddress Parity Fail Interrupt.
When this bit is high, the
bit is 1 after
When this bit is high, the
during auto-initialization. This bit is 1 after
RAM Initialization Fail Interrupt.
When this bit is high, the
location does not match its 2 corresponding serial EEPROM locations. This bit is 1 after
reset and cannot be reset by host register write.
Bit for Interrupt Type
MR
Don’t Care
master reset and cannot be reset by host register write.
Reset
Reset
INTHW
Set
Set
INTMES
HOLT INTEGRATED CIRCUITS
INTHW
INTHW
INTHW
HI-6120, HI-6121
INTHW
INTHW
output is asserted and the Interrupt Log is updated each time an incorrect
interrupt output assertion. See next section entitled “Pending Interrupt
interrupt output is asserted and the TTINT1 bit is set in the Pending
interrupt output is asserted and the TTINT0 bit is set in the Pending
interrupt is asserted when RT address parity error is detected.
interrupt is asserted if serial EEPROM checksum failure occurs
interrupt is asserted after auto-initialization if an initialized RAM
21
in Pending Interrupt Register
Effect on Corresponding Bit
Pending Int. Register bit is set
Pending Int. Register bit is set
Pending Int. Register bit is set
MR
master reset and cannot be reset by host register write.
No Change
No Change
INTMES
Signal Generated?
Is Interrupt Output
output is asserted and the
Yes
Yes
No
No
No
escriptor table
The IXEQZ,
MR
master
This