HI-6121PQMF HOLTIC [Holt Integrated Circuits], HI-6121PQMF Datasheet - Page 39

• Manufacturer Part Number: HI-6121PQMF
• Description: MIL-STD-1553 Remote Terminal ICs
• Manufacturer: HOLTIC [Holt Integrated Circuits]

DESCRIPTOR TABLE, Cont.
1
0
TRANSMIT SUBADDRESS CONTROL WORD
Transmit Subaddress Control Words apply when a valid command word T/ bit equals one (transmit) and the subaddress field
has a value in the range of 1 to 30 (0x1E). The descriptor Control Word defines terminal command response and interrupt
behavior, and conveys activity status to the host. It is initialized by the host before terminal execution begins. Bits 8-11 cannot
be written by the host; these bits are updated by the device during terminal execution, that is, when Configuration Register 1
STEX bit equals 1. The host can write bits 0-2 and 4-7 only when STEX equals zero; bits 3,12 and 14-15 can be written
anytime. This register is cleared to 0x0000 by
BCAST bits. Following any host read cycle to the Control Word address, the DBAC bit is reset.
Bit No.
15
14
13
12
11
10
MSB
15 14 13 12 11 10 9
H
H
CIR2EN
CIR1EN
Mnemonic Function
IXEQZ
IWA
——
MKBUSY
DBAC
DPB
X
H
D1 D
Circular Buffer Mode 2 Enable.
Circular Buffer Mode 1 Enable.
The PPEN, CIR1EN and CIR2EN bits are initialized by the host to select buffer mode. This table
summarizes how buffer mode selection is encoded:
Interrupt When Index Equals Zero.
If the Interrupt Enable Register IXEQZ bit is high, assertion of this bit enables generation of an
interrupt for (a) subaddresses using indexed buffer mode when the INDX value decrements from 1 to
0, or (b) subaddresses using a circular buffer mode when the pre-determined number of messages
has been transacted. If enabled, upon completion of command processing that results in index = 0,
an IXEQZ interrupt is entered in the Pending Interrupt Register, output pin
the interrupt is registered in the Interrupt Log.
Interrupt When Accessed.
If the Interrupt Enable Register IWA bit is high,
the subaddress receives any valid transmit command.
processing, an IWA interrupt is entered in the Pending Interrupt Register, output pin
asserted
Not used.
Make Busy.
The host asserts the MKBUSY bit to respond with Busy status for commands to this transmit
subaddress. This bit is an alternative to globally applying Busy status for all valid commands, enabled
from the 1553 Status Bits Register. See that register description for additional information. When
Busy is asserted, data words are not transmitted and the DPB bit does not toggle after message
completion.
Descriptor Block Accessed.
Internal device logic asserts the DBAC bit upon completion of message processing. The host may
poll this bit to detect subaddress activity, instead of using host interrupts. This bit is reset to logic zero
by
Data Pointer B.
This status bit is maintained by the device and only applies in ping-pong buffer mode. This bit
D
MR
D
PPEN
8
master reset, SRST software reset or a host read cycle to this memory address.
1
0
0
0
H
7
, and the interrupt is registered in the Interrupt Log.
H
6
H
5
H
4
HOLT INTEGRATED CIRCUITS
H
3
MR
H
2
HI-6120, HI-6121
Don’t care
H
1
master reset. Software reset (SRST) clears just the DBAC, DPB and
CIR2EN
H
0
1
0
0
LSB
39
assertion of this bit enables interrupt generation when
R
D1
H
D
X
Bit maintained by host
Bit maintained by device
Bit set by device, reset by host read cycle
Bit is not used, may be logic 0 or 1
Don’t care
Don’t care
CIR1EN
If enabled, upon completion of
1
0
Indexed Single Buffer
INTMES
Circular Mode 2
Circular Mode 1
Buffer Mode
Ping-Pong
is asserted, and
INTMES
command
is