HI-6121PQMF HOLTIC [Holt Integrated Circuits], HI-6121PQMF Datasheet - Page 19

• Manufacturer Part Number: HI-6121PQMF
• Description: MIL-STD-1553 Remote Terminal ICs
• Manufacturer: HOLTIC [Holt Integrated Circuits]

REGISTERS, Cont.
The binary 01 and 10 combinations of the MCOPT2 and MCOPT3 bits support certain extended subaddressing schemes. If
the MCOPT3-MCOPT2 bits equal 01, the received data word is automatically loaded into the Time-Tag counter
order bit of the received data word (bit 0) equals 0.
automatically loaded into the Time-Tag counter
broadcast MC17 commands, the counter load occurs before status word transmission. .
INTERRUPT LOG ADDRESS REGISTER
This 16-bit register is Read-Only and is fully maintained by HI-6120 logic. The register contains 0x0040 after
reset but is not affected by SRST software reset. Bits 7:0 contain an address pointer for the 32-word Interrupt Log Buffer
located in shared RAM. The value in Interrupt Log Address register bits 7:0 indicates the storage address where interrupt
information words will be stored for the next occurring interrupt, 0x40 - 0x5E. The value is always even since two words are
stored for each interrupt.
Bits 15:8 contain a count value for the number of interrupts logged (0 - 255) since the Interrupt Log Address Register was last
read. The count increment stops at 255. Bits 15:8 are reset automatically after this register is read by the host.
To help the host process interrupts, the device maintains information from the 16 most recent interrupts in a 32-word ring buffer
in shared RAM, found at address range 0x0040 to 0x005F. Each interrupt stores two information words: the Interrupt
Identification Word (IIW) identifies the interrupt type(s) that occurred; the Interrupt Address Word (IAW) identifies the interrupt
source. For interrupts that result from message processing, the IAW contains the 16-bit address of the command’s Control
Word in the Descriptor Table. For hardware interrupts, the IAW value is 0x0000.
After
0x40. During terminal operation, the host can read bits 15:8 to see the number of interrupts logged in the buffer since the last
read operation upon the register. Information words for the sixteenth interrupt are stored in buffer addresses 0x005E and
0x005F, and the Interrupt Log Address “rolls over” to read 0x40, where interrupt information for the seventeenth interrupt will be
stored. For further information on interrupts, see descriptions for the Interrupt Enable register, the Pending Interrupt register,
and see the later section entitled “Interrupt Management”.
CURRENT MESSAGE INFORMATION WORD ADDRESS REGISTER
This 16-bit register is Read-Only and is fully maintained by the device. This register is cleared after
not affected by SRST software reset. Also see “Current Control Word Address” register, 0x0004.
Bit No.
15-0
MEMORY ADDRESS POINTER REGISTER (HI-6121 ONLY)
This register is Read-Write and is cleared after
maintained by the host. The contained value is a memory address used when fulfilling RAM or register read or write operations
via the HI-6121 Serial Peripheral Interface (SPI). See data sheet section, ”Host Serial Peripheral Interface (SPI)” for further
details. For HI-6120 devices, writes to this address have no effect; the address reads back 0x0000 if a host read cycle occurs.
MSB
MSB
MR
15 14 13 12 11 10 9
15 14 13 12 11 10 9
C
A
master reset, the device automatically resets this register to 0x0040, an interrupt count of zero and log address of
C
A
Mnemonic Function
MIWA15:0 Current Message Information Word Address Register
CURRENT MSG INFO WORD ADDRESS 15:0
C
A
INTERRUPT
COUNT 7:0
C
A
C
A
C
A
This register contains the data buffer address for the last command’s Message Information Word, or
MIW, corresponding to the current command stored in the Current Command Register (0x0003).
This register is updated 5us after the ACTIVE output is asserted. Bit 15 is MSB.
C
A
C
A
8
8
A
0
7
7
A
1
6
6
INTERRUPT LOG
ADDRESS 7:0
A
0
5
5
A
A
4
4
HOLT INTEGRATED CIRCUITS
MR
A
A
3
3
if the low order bit of the received data word (bit 0) equals 1.
A
A
pin master reset, but is not affected by SRST software reset. This register is
2
2
HI-6120, HI-6121
(0x0009)
A
A
1
1
A
0
0
0
If the MCOPT3-MCOPT2 bits equal 10, the received data word is
LSB
LSB
19
(0x000F)
(0x000A)
MR
pin master reset, but is
MR
pin master
if the low
For non-