K9K1G08U0A Samsung semiconductor, K9K1G08U0A Datasheet - Page 31

• Manufacturer Part Number: K9K1G08U0A
• Description: 128M x 8 Bit / 64M x 16 Bit NAND Flash Memory
• Manufacturer: Samsung semiconductor

Device Operation
PAGE READ
Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00h to the command reg-
ister along with four address cycles. Once the command is latched, it does not need to be written for the following page read opera-
tion. Three types of operations are available : random read, serial page read and sequential row read.
The random read mode is enabled when the page address is changed. The 528 bytes of data within the selected page are trans-
ferred to the data registers in less than 12 s(t
ing the output of R/B pin. Once the data in a page is loaded into the registers, they may be read out in 50ns(1.8V device : 60ns)
cycle time by sequentially pulsing RE. High to low transitions of the RE clock output the data stating from the selected column
address up to the last column address.
After the data of last column address is clocked out, the next page is automatically selected for sequential row read.
Waiting 12 s again allows reading the selected page. The sequential row read operation is terminated by bringing CE high. The
way the Read1 and Read2 commands work is like a pointer set to either the main area or the spare area. The spare area of bytes
512 to 527 may be selectively accessed by writing the Read2 command. Addresses A
area while addresses A
sequential row read as in Read1 operation and spare sixteen bytes of each page may be sequentially read. The Read1 com-
mand(00h/01h) is needed to move the pointer back to the main area. Figures 9 to 12 show typical sequence and timings for each
read operation.
Figure 9. Read1 Operation
K9K1G08Q0A
K9K1G08U0A
CLE
CE
WE
ALE
R/B
RE
I/O
0
~
7
00h
* After data access on 2nd half array by 01h command, the start pointer is automatically moved to 1st half
array (00h) at next cycle.
K9K1G16Q0A
K9K1G16U0A
4
to A
A
0
7
Start Add.(4Cycle)
~ A
are ignored. Unless the operation is aborted, the page address is automatically incremented for
7
& A
9
~ A
26
R
1st half array
). The system controller can detect the completion of this data transfer(tR) by analyz-
(00h Command)
Data Field
t
R
2st half array
31
Spare Field
0
to A
1st half array
Data Output(Sequential)
3
set the starting address of the spare
(01h Command)*
Data Field
FLASH MEMORY
2st half array
Preliminary
Spare Field