BT848 ETC, BT848 Datasheet - Page 117
BT848
Manufacturer Part Number
BT848
Description
Single-Chip Video Capture for PCI
Manufacturer
ETC
Datasheet
1.BT848.pdf
(141 pages)
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Bt848/848A/849A
Single-Chip Video Capture for PCI
Video Timing Control
Memory Mapped Location 0x6C – Even Field (E_VTC)
Memory Mapped Location 0xEC – Odd Field (O_VTC)
Upon reset, it is initialized to 0x00. VFILT(0) is the least significant bit.
Brooktree
Bits
[6:2]
[1:0]
[7]
Type
RW
RW
RW
®
Default
0
00000
00
Name
HSFMT
HSFMT
Reserved
VFILT
Description
This bit selects between a single-pixel-wide HRESET and the standard
64-clock-wide HRESET.
of taps must be chosen in conjunction with the horizontal scale factor to
ensure the needed data does not overflow the internal FIFO.
settings and equations apply:
settings and equations apply:
These bits should only be written with a logical zero.
These bits control the number of taps in the Vertical Scaling Filter. The number
0
1
1
If the YCOMB bit in the VSCALE_HI register is a logical one, the following
00* = 2-tap
01
10
11
If the YCOMB bit in the VSCALE_HI register is a logical zero, the following
00* = 2-tap interpolation only. See Note 1.
01
10
11
Note 1: Available at all resolutions.
Note 2: Only available if scaling to less than 385 horizontal active pixels
Note 3: Only available if scaling to less than 193 horizontal active pixels
= HRESET is 64 CLKx1 cycles wide
= HRESET is 1 pixel wide
= HRESET is 32 CLKx1 cycles wide
= 3-tap
= 4-tap
= 5-tap
= 2-tap
= 3-tap
= 4-tap
(CIF or smaller).
(QCIF or smaller).
L848A_A
1
-- - 1
2
1
-- - 1
4
1
-- - 1
8
----- - 1
16
1
-- - 1
2
1
-- - 1
4
1
-- - 1
8
1
+
+
+
+
+
+
+
Z
2Z
3Z
Z
2Z
3Z
4Z
1 –
1 –
1 –
1 –
1 –
1 –
1 –
+
+
+
+
+
Z
3Z
Z
3Z
See Note 1.
and 2-tap interpolation. See Note 2.
6Z
2 –
2 –
2 –
2 –
2 –
+
+
+
Z
Z
See Note 2.
and 2-tap interpolation. See Note 3.
4Z
3 –
3 –
3 –
+
See Note 3.
See Note 3.
and 2-tap interpolation.
Z
C
4 –
ONTROL
See Note 3.
R
EGISTER
Video Timing Control
D
EFINITIONS
107
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