BT848 ETC, BT848 Datasheet - Page 127

• Manufacturer Part Number: BT848
• Description: Single-Chip Video Capture for PCI
• Manufacturer: ETC

Bt848/848A/849A
Single-Chip Video Capture for PCI
I
Memory Mapped Location 0x110
The data bytes can be read back after writing if I2CDIV is set to 0 (software drive mode). Otherwise, since the register
will be in shift mode during I2C circuit mode, the read data will be different from the data written to the register. The
data read from the slave will be stable after issuing a read slave transaction and I2CDONE is set.
Brooktree
2
Bits
[31:24]
[23:16]
C Data/Control
[15:8]
[7:4]
[3]
[2]
[1]
[0]
Type
®
RW
RW
RW
RW
RW
RW
RW
RW
Default
00000
0
0
1
1
Name
I2CDB0
I2CDB1
I2CDB2
I2CDIV
I2CSYNC
I2CW3B
I2CSCL
I2CSDA
Description
First byte sent in an I
chip 7-bit address and the R/W bit.
Second byte sent in an I
Third byte sent in an I
a read transaction, this byte register will contain the data read from
the slave.
Programmable divider after PCI clock/16 for SDA/SCL bit stream gen-
eration. This value must be set to zero for software mode.
A value of 1 enables bit-level clock synchronization which allows the
slave to insert wait states.
A value of 0 indicates a write transaction is to consist of sending two
bytes I2CDB(0–1), while a value of 1 indicates a 3-byte write trans-
mission.
A value of 1 releases the SCL output, and a 0 forces the SCL output
low. This bit must be set to a 1 during hardware mode. This override is
for direct software control of the bus. Reading this bit provides access
to the buffered SCL input pin.
A value of 1 releases the SDA output, and a 0 forces the SDA output
low. This bit must be set to a 1 during hardware mode. This override is
for direct software control of the bus. Reading this bit provides access
to the buffered SDA input pin.
L848A_A
2
2
C transaction. Typically this will be the base or
C write transaction, usually the data byte. After
2
C write transaction, usually a sub-address.
C
ONTROL
R
EGISTER
I
2
C Data/Control
D
EFINITIONS
117