BT848 ETC, BT848 Datasheet - Page 99

• Manufacturer Part Number: BT848
• Description: Single-Chip Video Capture for PCI
• Manufacturer: ETC

Bt848/848A/849A
Single-Chip Video Capture for PCI
Interrupt Line, Interrupt Pin, Min_Gnt, Max_Lat Register
PCI Configuration Header Location 0x3C
Min_Gnt and Max_Lat values are dependent on target performance (TRDY) and video mode (scale factors and color
format). These values were chosen for best case target (0 wait-state) and worst-case video delivery (full-resolution
32-bit RGB).
Brooktree
Bits
[31:25]
[24:16]
[15:8]
[7:0]
Type
®
RW
RO
RO
RO
Default
0x28
0x10
0x01
Name
Max_Lat
Min_Gnt
Interrupt Pin
Interrupt Line
L848A_A
Description
Require bus access every 8.5 S, at a minimum, in units of
250nS. Affects the desired settings for the latency timer value.
Desire a minimum grant burst period of 4 S to empty data FIFO,
in units of 250nS. Affects the desired settings for the latency timer
value. Set for 128 dwords, with 0 wait states.
Bt848 interrupt pin is connected to INTA, the only one usable by a
single function device.
The Interrupt Line register communicates interrupt line routing
information between the POST code and the device driver. The
POST code initializes this register with a value specifying to which
input (IRQ) of the system interrupt controller the Bt848 interrupt
pin is connected. Device drivers can use this value to determine
interrupt priority and vector information.
Interrupt Line, Interrupt Pin, Min_Gnt, Max_Lat Register
C
ONTROL
R
EGISTER
D
EFINITIONS
89