BT848 ETC, BT848 Datasheet - Page 18

• Manufacturer Part Number: BT848
• Description: Single-Chip Video Capture for PCI
• Manufacturer: ETC

F
Pin Descriptions
Table 2. Pin Descriptions Grouped by Pin Function (2 of 6)
8
UNCTIONAL
Pin #
51
42
43
44
45
46
49
14
8
50
See PCI Specification 2.1 for further documentation
D
ESCRIPTION
Pin Name
PAR
FRAME
IRDY
TRDY
DEVSEL
STOP
PERR
REQ
INTA
SERR
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
Signal
Parity
Cycle Frame
Initiator Ready
Target Ready
Device Select
Stop
Parity Error
Request
Interrupt A
System Error
L848A_A
Description
This three-state, bi-directional, I/O pin provides even parity
across AD[31:0] and CBE[3:0]. This means that the number
of 1’s on PAR, AD[31:0], and CBE[3:0] equals an even num-
ber.
For data phases, PAR is stable and valid one clock after
either TRDY is asserted on a read or IRDY is asserted on a
write. Once valid, PAR remains valid until one clock after the
completion of the current data phase. PAR and AD[31:0] have
the same timing, but PAR is delayed by one clock. The target
drives PAR for read data phases; the master drives PAR for
address and write data phases.
This sustained three-state signal is driven by the current
master to indicate the beginning and duration of an access.
FRAME is asserted to signal the beginning of a bus transac-
tion. Data transfer continues throughout assertion. At deas-
sertion, the transaction is in the final data phase.
This sustained three-state signal indicates the bus master’s
readiness to complete the current data phase.
and TRDY are asserted, a data phase is completed on that
clock. During a read, IRDY indicates when the initiator is
ready to accept data. During a write, IRDY indicates when the
initiator has placed valid data on AD[31:0]. Wait cycles are
inserted until both IRDY and TRDY are asserted together.
This sustained three-state signal indicates the target’s readi-
ness to complete the current data phase.
and TRDY are asserted, a data phase is completed on that
clock. During a read, TRDY indicates when the target is pre-
senting data. During a write, TRDY indicates when the target
is ready to accept the data. Wait cycles are inserted until both
IRDY and TRDY are asserted together.
This sustained three-state signal indicates device selection.
When actively driven, DEVSEL indicates the driving device
has decoded its address as the target of the current access.
This sustained three-state signal indicates the target is
requesting the master to stop the current transaction.
Report data parity error.
Agent desires bus.
This signal is an open drain interrupt output.
Report address parity error. Open drain.
PAR is stable and valid one clock after the address phase.
IRDY is used in conjunction with TRDY. When both IRDY
IRDY is used in conjunction with TRDY. When both IRDY
Single-Chip Video Capture for PCI
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