dsPIC33FJ32MC104-I/PT Microchip Technology, dsPIC33FJ32MC104-I/PT Datasheet - Page 142

• Manufacturer Part Number: dsPIC33FJ32MC104-I/PT
• Description: Digital Signal Processors & Controllers - DSP, DSC 16bit Mtr Cnt Fam 16 MIPS 32KBFLSH 2KBRAM
• Manufacturer: Microchip Technology
• Type: dsPIC33FJ32(GP/MC)101/102/104r

Specifications of dsPIC33FJ32MC104-I/PT

• Rohs: yes
• Core: dsPIC33F
• Data Bus Width: 16 bit
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Maximum Clock Frequency: 7.37 MHz, 32 kHz
• Number Of Programmable I/os: 35
• Number Of Timers: 5 x 16-bit, 2 x 32-bit
• Device Million Instructions Per Second: 16 MIPs
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Package / Case: TQFP-44
• Mounting Style: SMD/SMT
• Family / Core: dsPIC33FJ32(GP/MC)101/102/104
• Interface Type: I2C, SPI, UART
• Minimum Operating Temperature: - 40 C
• On-chip Adc: Yes
• Product: DSPs
• Program Memory Type: Flash
• Supply Current: 10 mA

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
10.4
Peripheral Pin Select configuration enables peripheral
set selection and placement on a wide range of I/O
pins. By increasing the pinout options available on a
particular device, programmers can better tailor the
microcontroller to their entire application, rather than
trimming the application to fit the device.
The Peripheral Pin Select configuration feature oper-
ates over a fixed subset of digital I/O pins. Program-
mers can independently map the input and/or output
of most digital peripherals to any one of these I/O
pins. Peripheral Pin Select is performed in software,
and generally does not require the device to be
reprogrammed. Hardware safeguards are included
that prevent accidental or spurious changes to the
peripheral mapping, once it has been established.
10.4.1
The Peripheral Pin Select feature is used with a range
of up to 16 pins. The number of available pins depends
on the particular device and its pin count. Pins that
support the Peripheral Pin Select feature include the
designation “RPn” in their full pin designation, where
“RP” designates a remappable peripheral and “n” is the
remappable pin number.
10.4.2
Peripheral Pin Select features are controlled through
two sets of Special Function Registers: one to map
peripheral inputs and one to map outputs. Because
they are separately controlled, a particular peripheral’s
input and output (if the peripheral has both) can be
placed on any selectable function pin without
constraint.
The association of a peripheral to a peripheral select-
able pin is handled in two different ways, depending on
whether an input or output is being mapped.
DS70652E-page 142
Peripheral Pin Select (PPS)
AVAILABLE PINS
CONTROLLING PERIPHERAL PIN
SELECT
10.4.2.1
The inputs of the Peripheral Pin Select options are
mapped on the basis of the peripheral. A control
register associated with a peripheral dictates the pin it
will be mapped to. The RPINRx registers are used to
configure peripheral input mapping (see
through
of 5-bit fields, with each set associated with one of the
remappable
peripheral’s bit field with an appropriate 5-bit value
maps the RPn pin with that value to that peripheral.
For any given device, the valid range of values for any
bit field corresponds to the maximum number of
Peripheral Pin Selections supported by the device.
Figure 10-2
U1RX input.
FIGURE 10-2:
Note:
RP 25
RP0
RP1
RP2
Register
For input mapping only, the Peripheral Pin
Select (PPS) functionality does not have
priority over the TRISx settings. There-
fore, when configuring the RPx pin for
input, the corresponding bit in the TRISx
register must also be configured for input
(i.e., set to ‘1’).
Illustrates remappable pin selection for
Input Mapping
peripherals.
10-10). Each register contains sets
 2011-2012 Microchip Technology Inc.
REMAPPABLE MUX
INPUT FOR U1RX
U1RXR<4:0>
0
1
2
25
Programming
U1RX Input
to Peripheral
Register 10-1
a
given