dsPIC33FJ32MC104-I/PT Microchip Technology, dsPIC33FJ32MC104-I/PT Datasheet - Page 173

• Manufacturer Part Number: dsPIC33FJ32MC104-I/PT
• Description: Digital Signal Processors & Controllers - DSP, DSC 16bit Mtr Cnt Fam 16 MIPS 32KBFLSH 2KBRAM
• Manufacturer: Microchip Technology
• Type: dsPIC33FJ32(GP/MC)101/102/104r

Specifications of dsPIC33FJ32MC104-I/PT

• Rohs: yes
• Core: dsPIC33F
• Data Bus Width: 16 bit
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Maximum Clock Frequency: 7.37 MHz, 32 kHz
• Number Of Programmable I/os: 35
• Number Of Timers: 5 x 16-bit, 2 x 32-bit
• Device Million Instructions Per Second: 16 MIPs
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Package / Case: TQFP-44
• Mounting Style: SMD/SMT
• Family / Core: dsPIC33FJ32(GP/MC)101/102/104
• Interface Type: I2C, SPI, UART
• Minimum Operating Temperature: - 40 C
• On-chip Adc: Yes
• Product: DSPs
• Program Memory Type: Flash
• Supply Current: 10 mA

13.0
The input capture module is useful in applications
requiring
measurement. The dsPIC33FJ16(GP/MC)101/102
and
support up to three input capture channels.
FIGURE 13-1:
 2011-2012 Microchip Technology Inc.
Note 1: This data sheet summarizes the features
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
ICx Pin
Note: An ‘x’ in a signal, register or bit name denotes the number of the capture channel.
dsPIC33FJ32(GP/MC)101/102/104
2: Some registers and associated bits
INPUT CAPTURE
of
and dsPIC33FJ32(GP/MC)101/102/104
family devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 12. “Input
Capture” (DS70198) in the “dsPIC33F/
PIC24H Family Reference Manual”,
which is available from the Microchip web
site (www.microchip.com).
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization”
this data sheet for device-specific register
and bit information.
frequency
Prescaler
(1, 4, 16)
the
Counter
3
dsPIC33FJ16(GP/MC)101/102
INPUT CAPTURE BLOCK DIAGRAM
System Bus
ICxCON
ICM<2:0> (ICxCON<2:0>)
Mode Select
(period)
ICOV, ICBNE (ICxCON<4:3>)
Edge Detection Logic
ICI<1:0>
Clock Synchronizer
and
and
devices
pulse
in
(in IFSn Register)
Set Flag ICxIF
Interrupt
Logic
The input capture module captures the 16-bit value of
the selected Time Base register when an event occurs
at the ICx pin. The events that cause a capture event
are listed below in three categories:
1.
2.
3.
Each input capture channel can select one of two
16-bit timers (Timer2 or Timer3) for the time base.
The selected timer can use either an internal or
external clock.
Other operational features include:
• Device wake-up from capture pin during CPU
• Interrupt on input capture event
• 4-word FIFO buffer for capture values:
• Use of input capture to provide additional sources
Sleep and Idle modes
- Interrupt optionally generated after 1, 2, 3 or
of external interrupts
Simple Capture Event modes:
• Capture timer value on every falling edge of
• Capture timer value on every rising edge of
Capture timer value on every edge (rising and
falling)
Prescaler Capture Event modes:
• Capture timer value on every 4th rising edge
• Capture timer value on every 16th rising
4 buffer locations are filled
input at ICx pin
input at ICx pin
of input at ICx pin
edge of input at ICx pin
R/W Logic
FIFO
From 16-Bit Timers
TMR2 TMR3
1
ICxBUF
16
0
DS70652E-page 173
16
ICTMR
(ICxCON<7>)