dsPIC33FJ32MC104-I/PT Microchip Technology, dsPIC33FJ32MC104-I/PT Datasheet - Page 204
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dsPIC33FJ32MC104-I/PT
Manufacturer Part Number
dsPIC33FJ32MC104-I/PT
Description
Digital Signal Processors & Controllers - DSP, DSC 16bit Mtr Cnt Fam 16 MIPS 32KBFLSH 2KBRAM
Manufacturer
Microchip Technology
Type
dsPIC33FJ32(GP/MC)101/102/104r
Datasheet
1.DSPIC33FJ32GP102-ISO.pdf
(386 pages)
Specifications of dsPIC33FJ32MC104-I/PT
Rohs
yes
Core
dsPIC33F
Data Bus Width
16 bit
Program Memory Size
32 KB
Data Ram Size
2 KB
Maximum Clock Frequency
7.37 MHz, 32 kHz
Number Of Programmable I/os
35
Number Of Timers
5 x 16-bit, 2 x 32-bit
Device Million Instructions Per Second
16 MIPs
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 125 C
Package / Case
TQFP-44
Mounting Style
SMD/SMT
Family / Core
dsPIC33FJ32(GP/MC)101/102/104
Interface Type
I2C, SPI, UART
Minimum Operating Temperature
- 40 C
On-chip Adc
Yes
Product
DSPs
Program Memory Type
Flash
Supply Current
10 mA
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC33FJ32MC104-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- Current page: 204 of 386
- Download datasheet (5Mb)
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
REGISTER 17-1:
DS70652E-page 204
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
STREN: SCLx Clock Stretch Enable bit (when operating as I
Used in conjunction with the SCLREL bit.
1 = Enables software or receives clock stretching
0 = Disables software or receives clock stretching
ACKDT: Acknowledge Data bit (when operating as I
Value that will be transmitted when the software initiates an Acknowledge sequence.
1 = Sends NACK during Acknowledge
0 = Sends ACK during Acknowledge
ACKEN: Acknowledge Sequence Enable bit (when operating as I
1 = Initiates Acknowledge sequence on SDAx and SCLx pins and transmits ACKDT data bit; hardware
0 = Acknowledge sequence is not in progress
RCEN: Receive Enable bit (when operating as I
1 = Enables Receive mode for I
0 = Receive sequence is not in progress
PEN: Stop Condition Enable bit (when operating as I
1 = Initiates Stop condition on SDAx and SCLx pins; hardware clears at end of the master Stop sequence
0 = Stop condition not in progress
RSEN: Repeated Start Condition Enable bit (when operating as I
1 = Initiates Repeated Start condition on SDAx and SCLx pins; hardware clears at end of the master
0 = Repeated Start condition is not in progress
SEN: Start Condition Enable bit (when operating as I
1 = Initiates Start condition on SDAx and SCLx pins; hardware clears at end of master Start sequence
0 = Start condition is not in progress
clears at end of master Acknowledge sequence
Repeated Start sequence
I2CxCON: I2Cx CONTROL REGISTER (CONTINUED)
2
C; hardware clears at end of eighth bit of the master receive data byte.
2
C master)
2
2
2
C master, applicable during master receive)
C master)
C master)
2
C slave)
2
C master, applicable during master receive)
2
C master)
2011-2012 Microchip Technology Inc.
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