dsPIC33FJ32MC104-I/PT Microchip Technology, dsPIC33FJ32MC104-I/PT Datasheet - Page 196
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dsPIC33FJ32MC104-I/PT
Manufacturer Part Number
dsPIC33FJ32MC104-I/PT
Description
Digital Signal Processors & Controllers - DSP, DSC 16bit Mtr Cnt Fam 16 MIPS 32KBFLSH 2KBRAM
Manufacturer
Microchip Technology
Type
dsPIC33FJ32(GP/MC)101/102/104r
Datasheet
1.DSPIC33FJ32GP102-ISO.pdf
(386 pages)
Specifications of dsPIC33FJ32MC104-I/PT
Rohs
yes
Core
dsPIC33F
Data Bus Width
16 bit
Program Memory Size
32 KB
Data Ram Size
2 KB
Maximum Clock Frequency
7.37 MHz, 32 kHz
Number Of Programmable I/os
35
Number Of Timers
5 x 16-bit, 2 x 32-bit
Device Million Instructions Per Second
16 MIPs
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 125 C
Package / Case
TQFP-44
Mounting Style
SMD/SMT
Family / Core
dsPIC33FJ32(GP/MC)101/102/104
Interface Type
I2C, SPI, UART
Minimum Operating Temperature
- 40 C
On-chip Adc
Yes
Product
DSPs
Program Memory Type
Flash
Supply Current
10 mA
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC33FJ32MC104-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- Current page: 196 of 386
- Download datasheet (5Mb)
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
16.1
1.
2.
3.
4.
5.
6.
DS70652E-page 196
Note:
Note:
Note:
In Frame mode, if there is a possibility that the
master may not be initialized before the slave:
a)
b)
In Non-Framed 3-Wire mode, (i.e., not using
SSx from a master):
a)
b)
FRMEN (SPIxCON2<15>) = 1 and SSEN
(SPIxCON1<7>) = 1 are exclusive and invalid.
In Frame mode, SCKx is continuous and the
Frame Sync pulse is active on the SSx pin,
which indicates the start of a data frame.
In Master mode only, set the SMP bit
(SPIxCON1<9>) to a ‘1’ for the fastest SPI data
rate possible. The SMP bit can only be set at the
same time or after the MSTEN bit (SPIxCON1<5>)
is set.
To avoid invalid slave read data to the master,
the user’s master software must ensure enough
time for slave software to fill its write buffer
before the user application initiates a master
write/read cycle. It is always advisable to pre-
load the SPIxBUF Transmit register in advance
of the next master transaction cycle. SPIxBUF is
transferred to the SPIx Shift register and is
empty once the data transmission begins.
The SPI related pins (SDI1, SDO1, SCK1) are
located at fixed positions in the dsPIC33FJ16(GP/
MC)10X devices. The same pins are remappable
in the dsPIC33FJ32(GP/MC)10X devices.
SPI Helpful Tips
If FRMPOL (SPIxCON2<13>) = 1, use a
pull-down resistor on SSx.
If FRMPOL = 0, use a pull-up resistor on SSx.
If CKP (SPIxCON1<6>) = 1, always place a
pull-up resistor on SSx.
If CKP = 0, always place a pull-down
resistor on SSx.
This insures that the first frame transmission
after initialization is not shifted or corrupted.
This will insure that during power-up and
initialization, the master/slave will not lose
sync due to an errant SCK transition that
would cause the slave to accumulate data
shift errors for both transmit and receive,
appearing as corrupted data.
Not all third-party devices support Frame
mode timing. Refer to the SPI electrical
characteristics for details.
16.2
Many useful resources are provided on the main prod-
uct page of the Microchip web site for the devices listed
in this data sheet. This product page, which can be
accessed using this link, contains the latest updates
and additional information.
16.2.1
• Section 18. “Serial Peripheral Interface (SPI)”
• Code Samples
• Application Notes
• Software Libraries
• Webinars
• All related “dsPIC33F/PIC24H Family Reference
• Development Tools
Note:
(DS70206) in the “dsPIC33F/PIC24H Family
Reference Manual”.
Manual” sections
SPI Resources
In the event you are not able to access
the product page using the link above,
enter this URL in your browser:
http://www.microchip.com/wwwproducts/
Devices.aspx?dDocName=en554109
KEY RESOURCES
2011-2012 Microchip Technology Inc.
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