MC9S12P64VQK Freescale Semiconductor, MC9S12P64VQK Datasheet - Page 207

• Manufacturer Part Number: MC9S12P64VQK
• Description: 16-bit Microcontrollers - MCU 16 BIT 64K FLASH
• Manufacturer: Freescale Semiconductor

Specifications of MC9S12P64VQK

• Rohs: yes
• Core: S12
• Processor Series: MC9S12P
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 64 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5 V
• Operating Temperature Range: - 40 C to 105 C
• Package / Case: QFP-80
• Mounting Style: SMD/SMT
• Interface Type: I2C, SCI, SPI
• Program Memory Type: Flash

7.3.2.2
The CPMUREFDIV register provides a finer granularity for the PLL multiplier steps when using the
external oscillator as reference.
Read: Anytime
Write: If PROT=0 (CPMUPROT register) and PLLSEL=1 (CPMUCLKS register), then write anytime.
Else write has no effect.
The REFFRQ[1:0] bits are used to configure the internal PLL filter for optimal stability and lock time. For
correct PLL operation the REFFRQ[1:0] bits have to be selected according to the actual REFCLK
frequency as shown in
If IRC1M is selected as REFCLK (OSCE=0) the PLL filter is fixed configured for the 1MHz <= f
2MHz range. The bits can still be written but will have no effect on the PLL filter configuration.
For OSCE=1, setting the REFFRQ[1:0] bits incorrectly can result in a non functional PLL (no locking
and/or insufficient stability).
Freescale Semiconductor
0x0035
Reset
If OSCLCP is enabled (OSCE=1)
If OSCLCP is disabled (OSCE=0)
W
R
S12CPMU Reference Divider Register (CPMUREFDIV)
0
7
REFFRQ[1:0]
Write to this register clears the LOCK and UPOSC status bits.
Table 7-2. Reference Clock Frequency Selection if OSC_LCP is enabled
Figure 7-5. S12CPMU Reference Divider Register (CPMUREFDIV)
Table
0
6
7-2.
REFCLK Frequency Ranges
1MHz <= f
6MHz < f
S12P-Family Reference Manual, Rev. 1.13
2MHz < f
0
0
5
f
REF
(OSCE=1)
REF
f REF
f REF
REF
>12MHz
REF
<= 12MHz
<= 6MHz
<= 2MHz
=
=
NOTE
------------------------------------
(
f IRC1M
0
0
4
REFDIV
f OSC
S12 Clock, Reset and Power Management Unit (S12CPMU)
+
1
)
1
3
REFFRQ[1:0]
00
01
10
11
1
2
REFDIV[3:0]
1
1
REF
1
0
<=
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