MC9S12P64VQK Freescale Semiconductor, MC9S12P64VQK Datasheet - Page 336

• Manufacturer Part Number: MC9S12P64VQK
• Description: 16-bit Microcontrollers - MCU 16 BIT 64K FLASH
• Manufacturer: Freescale Semiconductor

Specifications of MC9S12P64VQK

• Rohs: yes
• Core: S12
• Processor Series: MC9S12P
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 64 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5 V
• Operating Temperature Range: - 40 C to 105 C
• Package / Case: QFP-80
• Mounting Style: SMD/SMT
• Interface Type: I2C, SCI, SPI
• Program Memory Type: Flash

Pulse-Width Modulator (PWM8B6CV1) Block Description
10.3.2.2
The starting polarity of each PWM channel waveform is determined by the associated PPOLx bit in the
PWMPOL register. If the polarity bit is 1, the PWM channel output is high at the beginning of the cycle
and then goes low when the duty count is reached. Conversely, if the polarity bit is 0 the output starts low
and then goes high when the duty count is reached.
Read: anytime
Write: anytime
336
Module Base + 0x0001
PWME1
PWME0
PPOL5
PPOL4
Reset
Field
Field
1
0
5
4
W
R
Pulse Width Channel 1 Enable
0 Pulse width channel 1 is disabled.
1 Pulse width channel 1 is enabled. The pulse modulated signal becomes available at PWM, output bit 1 when
Pulse Width Channel 0 Enable
0 Pulse width channel 0 is disabled.
1 Pulse width channel 0 is enabled. The pulse modulated signal becomes available at PWM, output bit 0 when
Pulse Width Channel 5 Polarity
0 PWM channel 5 output is low at the beginning of the period, then goes high when the duty count is reached.
1 PWM channel 5 output is high at the beginning of the period, then goes low when the duty count is reached.
Pulse Width Channel 4 Polarity
0 PWM channel 4 output is low at the beginning of the period, then goes high when the duty count is reached.
1 PWM channel 4 output is high at the beginning of the period, then goes low when the duty count is reached.
PWM Polarity Register (PWMPOL)
0
0
7
its clock source begins its next cycle.
its clock source begins its next cycle. If CON01 = 1, then bit has no effect and PWM output line 0 is disabled.
PPOLx register bits can be written anytime. If the polarity is changed while
a PWM signal is being generated, a truncated or stretched pulse can occur
during the transition
= Unimplemented or Reserved
0
0
6
Table 10-2. PWME Field Descriptions (continued)
Figure 10-4. PWM Polarity Register (PWMPOL)
Table 10-3. PWMPOL Field Descriptions
S12P-Family Reference Manual, Rev. 1.13
PPOL5
0
5
PPOL4
NOTE
0
4
Description
Description
PPOL3
0
3
PPOL2
0
2
PPOL1
Freescale Semiconductor
0
1
PPOL0
0
0