C8051F964-A-GQ Silicon Labs, C8051F964-A-GQ Datasheet - Page 172

• Manufacturer Part Number: C8051F964-A-GQ
• Description: 8-bit Microcontrollers - MCU 64KB DC-DC LCD AES
• Manufacturer: Silicon Labs

Specifications of C8051F964-A-GQ

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 24.5 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.8 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: QFP-80
• Mounting Style: SMD/SMT

C8051F96x
SFR Definition 13.1. CRC1CN: CRC1 Control
SFR Page = 0x2; SFR Address = 0xBE; Not Bit-Addressable
172
Name
Reset
6:4
Bit
Type
7
3
2
1
0
Bit
Reserved
CLR
R/W
Name
SEED
DMA
FLIP
RST
INV
7
0
Reset.
Setting this bit to 1 will reset the CRC module and set the CRC results SFR to
the seed value as specified by the SEED bit. The CRC module should be reset
before starting a new CRC.
This bit is self-clearing.
DMA Mode.
Setting this bit will configure the CRC1 module for DMA mode.
Once a DMA channel has been configured to use accept peripheral requests
from CRC1, setting this bit will initiate a DMA CRC operation.
This bit should be cleared after each CRC DMA transfer.
Flip.
Setting this bit will flip the contents of the 16-bit CRC result SFRs.
(CRC0OUTH:CRC0OUTL)
This operation is normally performed only on the final CRC results.
This bit should be cleared before starting a new CRC computation.
Invert.
Setting this bit will invert the contents of the 16-bit CRC result SFR.
(CRC0OUTH:CRC0OUTL)
This operation is normally performed only on the final CRC results.
This bit should be cleared before starting a new CRC computation.
Seed Polarity.
If this bit is zero, a seed value or 0x0000 will be used.
If this bit is 1, a seed value of 0xFFFF will be used.
This bit should be set before setting the RST bit.
R
6
0
R
5
0
Rev. 0.5
R
4
0
Function
DMA
R/W
3
0
FLIP
R/W
2
0
R/W
INV
1
0
SEED
R/W
0
0