C8051F964-A-GQ Silicon Labs, C8051F964-A-GQ Datasheet - Page 345
C8051F964-A-GQ
Manufacturer Part Number
C8051F964-A-GQ
Description
8-bit Microcontrollers - MCU 64KB DC-DC LCD AES
Manufacturer
Silicon Labs
Datasheet
1.C8051F960-A-GQ.pdf
(492 pages)
Specifications of C8051F964-A-GQ
Rohs
yes
Core
8051
Processor Series
C8051
Data Bus Width
8 bit
Maximum Clock Frequency
24.5 MHz
Program Memory Size
64 KB
Data Ram Size
8 KB
On-chip Adc
Yes
Operating Supply Voltage
1.8 V to 3.8 V
Operating Temperature Range
- 40 C to + 85 C
Package / Case
QFP-80
Mounting Style
SMD/SMT
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26.5. Setting the LCD Refresh Rate
The clock to the LCD0 module is derived from the SmaRTClock and may be divided down according to the
settings in the LCD0CN register. The LCD refresh rate is derived from the LCD0 clock and can be pro-
grammed using the LCD0DIVH:LCD0DIVL registers. The LCD mux mode must be taken into account
when determining the prescaler value. See the LCD0DIVH/LCD0DIVL register descriptions for more
details. For maximum power savings, choose a slow LCD refresh rate and the minimum LCD0 clock fre-
quency. For the least flicker, choose a fast LCD refresh rate.
SFR Definition 26.8. LCD0CLKDIVH: LCD0 Refresh Rate Prescaler High Byte
SFR Page = 0x2; SFR Address = 0xAA
SFR Definition 26.9. LCD0CLKDIVL: LCD Refresh Rate Prescaler Low Byte
SFR Page = 0x2; SFR Address = 0xA9
Name
Reset
Name
Reset
Type
Type
7:2
1:0
7:0
Bit
Bit
Bit
Bit
LCD0DIV[9:8] LCD Refresh Rate Prescaler.
LCD0DIV[7:0] LCD Refresh Rate Prescaler.
Unused
R/W
Name
Name
7
0
7
0
Read = 000000. Write = Don’t Care.
Sets the LCD refresh rate according to the following equation:
Sets the LCD refresh rate according to the following equation:
R/W
6
0
6
0
LCD Refresh Rate
LCD Refresh Rate
R/W
5
0
5
0
=
=
---------------------------------------------------------------------------------- -
4 mux_mode
---------------------------------------------------------------------------------- -
4 mux_mode
Rev. 0.5
R/W
LCD0 Clock Frequency
LCD0DIV[7:0]
LCD0 Clock Frequency
4
0
4
0
R/W
Function
Function
R/W
LCD0DIV
LCD0DIV
3
0
3
0
+
+
1
1
R/W
2
0
2
0
C8051F96x
LCD0DIV[9:8]
1
0
1
0
R/W
0
0
0
0
345
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