C8051F964-A-GQ Silicon Labs, C8051F964-A-GQ Datasheet - Page 201
C8051F964-A-GQ
Manufacturer Part Number
C8051F964-A-GQ
Description
8-bit Microcontrollers - MCU 64KB DC-DC LCD AES
Manufacturer
Silicon Labs
Datasheet
1.C8051F960-A-GQ.pdf
(492 pages)
Specifications of C8051F964-A-GQ
Rohs
yes
Core
8051
Processor Series
C8051
Data Bus Width
8 bit
Maximum Clock Frequency
24.5 MHz
Program Memory Size
64 KB
Data Ram Size
8 KB
On-chip Adc
Yes
Operating Supply Voltage
1.8 V to 3.8 V
Operating Temperature Range
- 40 C to + 85 C
Package / Case
QFP-80
Mounting Style
SMD/SMT
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14.6.6.1. CTR Encryption using SFRs
If encrypting multiple blocks, increment the counter and repeat this process. It is not necessary reconfigure
the AES module for each block.
Disable the DMA by writing 0x00 to DMA0EN
Increment counter and repeat all steps for additional blocks
First Configure AES Module for CTR Block Cipher Mode Encryption
Repeat alternating write sequence 16 times
Write remaining encryption key bytes to AES0KIN for 192-bit and 256-bit decryption only.
Wait on AES done interrupt or poll bit 5 of AES0BCFG.
Read 16 encrypted bytes from the AES0YOUT sfr.
Reset AES module by writing 0x00 to AES0BCFG.
Configure the AES Module data flow for XOR on output data by writing 0x02 to the AES0DCFG sfr.
Write key size to bits 1 and 0 of the AES0BCFG.
Configure the AES core for encryption by setting bit 2 of AES0BCFG.
Enable the AES core by setting bit 3 of AES0BCFG.
Write plaintext byte to AES0BIN.
Write counter byte to AES0XIN
Write encryption key byte to AES0KIN.
Rev. 0.5
C8051F96x
201
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