LPC1112FHN33/202 NXP Semiconductors, LPC1112FHN33/202 Datasheet - Page 71

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LPC1112FHN33/202

Manufacturer Part Number
LPC1112FHN33/202
Description
ARM Microcontrollers - MCU CortexM0 32bit 16KB
Manufacturer
NXP Semiconductors
Datasheet

Specifications of LPC1112FHN33/202

Rohs
yes
Core
ARM Cortex M0
Data Bus Width
32 bit

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0
NXP Semiconductors
LPC111X
Product data sheet
Power measurements in Active, Sleep, and Deep-sleep modes were performed under the
following conditions (see LPC111x user manual):
Fig 27. Active mode: Typical supply current I
Configure all pins as GPIO with pull-up resistor disabled in the IOCONFIG block.
Configure GPIO pins as outputs using the GPIOnDIR registers.
Write 0 to all GPIOnDATA registers to drive the outputs LOW.
(mA)
I
DD
Conditions: T
disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks
disabled; internal pull-up resistors disabled; BOD disabled; low-current mode.
3 MHz - 6 MHz: system oscillator enabled; PLL, IRC disabled.
12 MHz: IRC enabled; system oscillator, PLL disabled.
24 MHz - 48 MHz: IRC disabled; system oscillator, PLL enabled.
system clock frequencies (for LPC111x/103/203/303/323/333)
8
6
4
2
0
1.8
All information provided in this document is subject to legal disclaimers.
amb
Rev. 8 — 20 February 2013
= 25 C; active mode entered executing code
2.1
2.4
LPC1110/11/12/13/14/15
DD
2.7
48 MHz
36 MHz
24 MHz
12 MHz
6 MHz
3 MHz
versus supply voltage V
32-bit ARM Cortex-M0 microcontroller
3
while(1){}
from flash; all peripherals
3.3
V
DD
© NXP B.V. 2013. All rights reserved.
DD
(V)
002aag922
for different
3.6
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