MK60DN512VMC10 Freescale Semiconductor, MK60DN512VMC10 Datasheet - Page 64

• Manufacturer Part Number: MK60DN512VMC10
• Description: ARM Microcontrollers - MCU Kinetis 2.x 512K
• Manufacturer: Freescale Semiconductor

Specifications of MK60DN512VMC10

• Rohs: yes
• Core: ARM Cortex M4
• Processor Series: MK60DN512
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 100 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: MAPBGA-121
• Mounting Style: SMD/SMT
• A/d Bit Size: 16 bit
• A/d Channels Available: 2
• Interface Type: CAN, I2C, I2S, SPI, UART, USB
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Timers: 2
• On-chip Dac: Yes
• Program Memory Type: Flash
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 1.71 V

Peripheral operating requirements and behaviors
6.8.11 I2S/SAI Switching Specifications
This section provides the AC timing for the I2S/SAI module in master mode (clocks are
driven) and slave mode (clocks are input). All timing is given for noninverted serial clock
polarity (TCR2[BCP] is 0, RCR2[BCP] is 0) and a noninverted frame sync (TCR4[FSP]
is 0, RCR4[FSP] is 0). If the polarity of the clock and/or the frame sync have been
inverted, all the timing remains valid by inverting the bit clock signal (BCLK) and/or the
frame sync (FS) signal shown in the following figures.
6.8.11.1 Normal Run, Wait and Stop mode performance over a limited
This section provides the operating performance over a limited operating voltage for the
device in Normal Run, Wait and Stop modes.
64
Num
SD6
SD7
SD8
SDHC_CLK
Output SDHC_CMD
Output SDHC_DAT[3:0]
Input SDHC_CMD
Input SDHC_DAT[3:0]
operating voltage range
Symbol
t
t
t
OD
ISU
IH
Table 46. SDHC switching specifications
SDHC output delay (output valid)
SDHC input setup time
SDHC input hold time
Description
SDHC input / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
K60 Sub-Family Data Sheet, Rev. 2, 12/2012.
SD3
SD6
(continued)
Figure 26. SDHC timing
SD2
SD7
SD8
SD1
Min.
-5
5
0
Freescale Semiconductor, Inc.
Max.
6.5
—
—
Unit
ns
ns
ns