MK60DN512VMC10 Freescale Semiconductor, MK60DN512VMC10 Datasheet - Page 69

• Manufacturer Part Number: MK60DN512VMC10
• Description: ARM Microcontrollers - MCU Kinetis 2.x 512K
• Manufacturer: Freescale Semiconductor

Specifications of MK60DN512VMC10

• Rohs: yes
• Core: ARM Cortex M4
• Processor Series: MK60DN512
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 100 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: MAPBGA-121
• Mounting Style: SMD/SMT
• A/d Bit Size: 16 bit
• A/d Channels Available: 2
• Interface Type: CAN, I2C, I2S, SPI, UART, USB
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Timers: 2
• On-chip Dac: Yes
• Program Memory Type: Flash
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 1.71 V

Table 51. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes (full voltage range)
Freescale Semiconductor, Inc.
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
I2S_MCLK (output)
I2S_TX_BCLK/
I2S_RX_BCLK (output)
I2S_TX_FS/
I2S_RX_FS (output)
I2S_TX_FS/
I2S_RX_FS (input)
I2S_TXD
I2S_RXD
Num.
Num.
Table 52. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full
(continued)
I2S_MCLK cycle time
I2S_MCLK pulse width high/low
I2S_TX_BCLK/I2S_RX_BCLK cycle time (output)
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
I2S_TX_BCLK to I2S_TXD valid
I2S_TX_BCLK to I2S_TXD invalid
I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK
Operating voltage
I2S_TX_BCLK/I2S_RX_BCLK cycle time (input)
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
(input)
voltage range)
S5
S7
Figure 31. I2S/SAI timing — master modes
Characteristic
Characteristic
S4
K60 Sub-Family Data Sheet, Rev. 2, 12/2012.
S9
S9
S1
Table continues on the next page...
S3
S2
S10
S4
S2
S8
62.5
45%
250
45%
—
0
—
0
45
0
1.71
250
45%
S7
Peripheral operating requirements and behaviors
Min.
Min.
—
55%
—
55%
45
—
45
—
—
—
3.6
—
55%
Max.
Max.
ns
MCLK period
ns
BCLK period
ns
ns
ns
ns
ns
ns
V
ns
MCLK period
Unit
Unit
S10
S6
S8
69